Differential Buffer Power Stage Without Bias Voltage Routing
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Solution Overview
Problem
Modern CMOS processes struggle to handle voltages higher than their typical operating levels, such as those encountered in battery-powered circuits, due to transistor breakdown voltage limitations, leading to routing difficulties and design challenges when integrating higher voltage blocks.
Innovation Solution
The implementation of a differential buffer circuit for both high and low side buffers eliminates the need for an intermediate bias voltage, allowing self-biasing and simplifying routing, while reducing noise and parasitics through smaller transistor usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If standard CMOS circuits are used to handle higher voltages, then voltage handling capability is improved, but transistor breakdown voltage limitations cause reliability deterioration
Solution Approach 1:
The power stage is divided into multiple buffers (first buffer, second buffer, third buffer) that operate at different voltage levels. Each buffer handles a portion of the voltage range, with the first buffer operating between Vbat and Vbias1, the second buffer between Vbias1 and Vbias2, and the third buffer between Vbias2 and Vss. This segmentation allows standard CMOS transistors to operate within their safe voltage limits while collectively handling the full high voltage range.
2Temperature
If cascode circuits or extended drain MOS transistors are used to handle higher voltages, then voltage handling capability is improved, but design complexity and routing difficulty increase
Solution Approach 1:
The circuit generates its own bias voltages (Vbias1 and Vbias2) internally through the buffer stages themselves, eliminating the need for external bias voltage generation and routing. The first buffer automatically generates Vbias1, which is then used to bias the second buffer, which in turn generates Vbias2 for the third buffer. This self-biasing approach simplifies the overall circuit design and reduces routing complexity.
3Adaptability or versatility
If multiple buffer stages are used to drive output transistors, then voltage level shifting capability is improved, but routing difficulty for bias voltage increases
Solution Approach 1:
The bias voltage generation function is merged with the buffer stages themselves. Each buffer stage not only performs voltage level shifting but also generates the bias voltage needed by the subsequent stage. This combination of functions eliminates the need for separate bias voltage generation circuits and their associated routing, simplifying the overall design while maintaining multi-stage voltage level shifting capability.
Data Source
AI summary
A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.