Differential Bus Driver Timing for Waveform Balance and Noise Reduction
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Solution Overview
Problem
Existing differential signal buses in in-vehicle and factory automation networks are prone to noise interference, which can affect the reliability and performance of connected devices.
Innovation Solution
A circuit device is designed to drive differential signal buses, featuring high-side and low-side transistors and a drive circuit with first and second delay circuits. These delay circuits set specific delay times for the rising and falling edges of drive signals, allowing for independent adjustment to reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If differential signal bus is used for in-vehicle and factory automation networks, then communication capability is improved, but noise interference increases
Solution Approach 1:
The patent applies preliminary action by pre-setting different delay times for rising edges and falling edges of drive signals. The delay circuits are configured in advance to compensate for waveform imbalances before they cause noise issues, thereby proactively preventing noise interference while maintaining differential signal transmission capability
2Productivity
If drive signals are transmitted to high-side and low-side transistors, then differential signal transmission is achieved, but waveform imbalance occurs causing noise
Solution Approach 1:
The patent applies asymmetry by introducing different delay times for rising edges and falling edges of drive signals. Instead of treating both edges symmetrically, the delay circuit is configured to apply asymmetric delay compensation, matching the different propagation characteristics of high-side and low-side transistors, thereby balancing the output waveforms and reducing noise
3Object-affected harmful factors
If delay circuits are added to balance waveforms, then noise is reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces delay circuits as intermediary elements between the drive circuit and the high-side/low-side transistors. These delay circuits act as mediators that adjust signal timing to balance waveforms. The delay circuits are implemented using standard delay elements and control signals, keeping the added complexity manageable while achieving effective noise reduction
Data Source
AI summary
A circuit device for driving a differential signal bus includes a high-side transistor between a power supply node and a first output terminal coupled to the differential signal bus, a low-side transistor between a ground node and a second output terminal coupled to the differential signal bus, and a drive circuit output a first drive signal to one of the gate of the high-side transistor and the gate of the low-side transistor and to output a second drive signal to the other of the gate of the high-side transistor and the gate of the low-side transistor. The drive circuit includes a first delay circuit sets a first delay time that is a delay time for the rising edge of the second drive signal, and a second delay circuit sets a second delay time that is a delay time for the falling edge of the second drive signal.