Differential Capacitive Sampling Circuit for Common-Mode Noise Rejection

The capacitive sampling circuit is segmented into separate first and second capacitive sampling circuits, each handling one differential input signal. This segmentation allows independent control and optimization of each sampling path, enabling effective common mode noise rejection while maintaining manageable circuit complexity through modular architecture.

The patent transitions from single-ended sampling to fully differential sampling by adding a second capacitive sampling circuit that mirrors the first. This dimensional expansion from one-dimensional to two-dimensional sampling architecture enables common mode noise cancellation through differential processing, improving CMRR without excessive complexity increase.

The first capacitor first plate switching block is designed to perform multiple functions: it can connect the first plate of sampling capacitors to either the first differential input terminal or reference voltage terminals depending on the operational state. This multi-functionality reduces the need for separate dedicated switches for each connection, thereby reducing overall switching block complexity while enabling fully differential sampling.

The switching blocks are designed to dynamically reconfigure their connections based on the operational state (sampling or conversion). During sampling, they connect to differential inputs; during conversion, they connect to reference voltages. This dynamic reconfiguration allows a single switching block to handle multiple operational requirements, reducing static complexity while achieving high measurement precision.

The capacitive sampling circuit operates in periodic cycles alternating between sampling state and conversion state. During the sampling state, capacitors are connected to differential inputs to capture the signal. During the conversion state, they are disconnected and connected to reference voltages to prevent common mode noise propagation. This periodic switching ensures both accurate signal sampling and effective common mode noise reduction at different time intervals.

The circuit performs preliminary sampling action by connecting capacitors to differential inputs during the sampling state to capture the input signal before conversion begins. This preliminary action ensures the signal is accurately captured and stored on the capacitors before the conversion state begins, at which point the capacitors are disconnected from differential inputs to prevent common mode noise propagation during the conversion process.