Differential Logic Circuit Anomaly Detection for Cryptography
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Solution Overview
Problem
Cryptography circuits in mass-market devices with low calculation power are vulnerable to attacks such as timing attacks, Simple Power Analysis (SPA), Differential Power Analysis (DPA), and fault injection attacks due to physical imperfections, which existing countermeasures like redundancy and additional hardware components increase costs.
Innovation Solution
A method and circuit using differential logic to detect anomalies by processing logic variables in pre-charge and evaluation phases, employing OR and XNOR gates to identify non-consistent states, and utilizing multiplexers to select signals for anomaly detection, integrated into cryptography circuits to enhance security without additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy countermeasures are implemented to detect fault injection attacks, then security against fault attacks is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the fault detection function with the existing differential logic structure by utilizing the inherent redundancy of dual-rail logic. The detection mechanism is integrated into the normal operation of the circuit, combining computation and verification in a unified structure rather than adding separate redundant components.
Solution Approach 2:
The differential logic circuit performs self-verification through its inherent redundancy. The dual-rail logic naturally provides detection capability without requiring external monitoring circuits or additional redundancy mechanisms, allowing the circuit to detect faults autonomously using its own structural properties.
2Reliability
If additional hardware components are added to protect against attacks, then security is improved, but manufacturing cost increases
Solution Approach 1:
The dual-rail logic structure serves multiple functions simultaneously: it performs the cryptographic computation and provides fault detection capability. This multi-functionality eliminates the need for separate protection hardware, reducing manufacturing complexity and cost while maintaining security.
Solution Approach 2:
The circuit uses its own inherent redundancy to provide security functions, eliminating the need for additional protective hardware components. The dual-rail logic structure itself serves as both the computation medium and the detection mechanism, reducing manufacturing cost.
3Productivity
If timing optimization is implemented to improve processing speed, then calculation speed is improved, but vulnerability to timing attacks increases
Solution Approach 1:
The patent implements feedback through continuous monitoring of signal consistency in the dual-rail logic. Any timing variations or anomalies that could indicate timing attacks are detected through the inherent redundancy and fed back to trigger alert conditions, allowing the system to respond to timing attacks in real-time.
Solution Approach 2:
The patent converts the potential harm of timing variations into a beneficial detection signal. By using dual-rail logic with consistency checking, timing anomalies that could indicate attacks are transformed into detectable inconsistencies that trigger security responses, turning a vulnerability into a detection opportunity.
Data Source
AI summary
In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.