Differential Circuit Offset Suppression via Segmented Current Mirrors
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Solution Overview
Problem
Conventional differential circuits face challenges in suppressing offset, maintaining response speed, and reducing the number of elements, particularly when operating at lower power supply voltages, due to characteristic variations and manufacturing variations in transistors.
Innovation Solution
A differential circuit design that includes a first and second constant current circuit, a current mirror with transistors having short-circuited gates, and an adjusting portion with additional transistors and constant current circuits to adjust output currents based on input voltages, allowing for offset suppression and reduced power supply voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate widths of transistors are increased and/or gate lengths are decreased to increase gains and suppress offset, then manufacturing precision is improved, but response speeds are decreased due to increased mirror capacitances
Solution Approach 1:
The patent divides the differential circuit into multiple stages: a first differential circuit stage and a second differential circuit stage. Each stage has its own transistors and current mirrors. This segmentation allows the first stage to operate with smaller transistor sizes (faster response) while the second stage can use larger transistor sizes (better offset suppression), thus resolving the contradiction between response speed and offset suppression.
2Speed
If a multi-stage structure is adopted to increase total gain while decreasing gain of each transistor to reduce mirror capacitance, then response speed is improved, but the number of elements is increased
Solution Approach 1:
The patent combines the functions of multiple differential stages into a unified circuit architecture where the first and second differential circuit stages share common elements such as the constant current circuit and power supply connections. This merging approach reduces the total number of independent elements compared to a fully separate multi-stage design, while still achieving the benefits of staged gain multiplication and reduced mirror capacitance.
3Device complexity
If conventional differential circuit structures are used, then the number of elements is reduced, but offset cannot be effectively suppressed due to characteristic variations
Solution Approach 1:
The patent implements a feedback mechanism through the second current mirror that senses the output current from the first current mirror and adjusts the gate voltages of the second differential pair transistors accordingly. This feedback action compensates for characteristic variations and offsets, improving manufacturing precision without requiring a significant increase in the number of elements.
Data Source
AI summary
A differential circuit includes a first constant current circuit, a second constant current circuit having the same constant current value as the first constant current circuit, a current mirror including a first transistor having a current sink terminal connected to the first constant current circuit, a current drain terminal to which a first input voltage is applied, and a gate short-circuited to the current sink terminal, and a second transistor having a gate connected to the current sink terminal of the first transistor and a current drain terminal to which a second input voltage is applied, and a current output terminal connected to a connection node between a part in which a current based on an output current of the current mirror flows and the second constant current circuit.