Integrated Differential Clock Buffering for Low-Drift Multi-Output Clocks
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Solution Overview
Problem
As integration increases and input/output needs grow, providing reference clock signals to processor dies becomes impractical due to increased pin count and routing complexity, especially with differential clock signals, leading to performance risks from clock distribution techniques.
Innovation Solution
A fully integrated clock differential buffer (FICDB) is used to supply a high-quality reference clock signal to high-speed interconnects and processing cores, reducing performance risks by controlling reference clock drift and providing multiple reference clock pairs with adaptive PLL bandwidth and individual output enabling control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional external clock signals are provided to meet increasing reference clock needs, then the number of reference clock entries increases, but the number of pins and routing complexity become impractical
Solution Approach 1:
The patent combines multiple clock buffer functions into a single integrated clock buffer device. Instead of using multiple separate buffer components that would require multiple pins and complex routing, the invention integrates all buffering functions within one component that accepts a single differential clock input and provides multiple buffered clock outputs, thereby reducing pin count and simplifying routing while meeting increasing reference clock needs
Solution Approach 2:
The integrated clock buffer device performs multiple functions within a single component: it receives a differential clock input, buffers the signal, and provides multiple buffered clock outputs to different destinations. This multi-functional approach eliminates the need for separate buffer components for each clock output, directly addressing the contradiction by reducing the number of pins and routing complexity while maintaining the required number of reference clock entries
2Quantity of substance
If additional external clock signals are provided to meet increasing reference clock needs, then the number of reference clock entries increases, but the pin count becomes impractical
Solution Approach 1:
The patent combines multiple clock buffer functions into a single integrated clock buffer device. Instead of using multiple separate buffer components that would require multiple pins and complex routing, the invention integrates all buffering functions within one component that accepts a single differential clock input and provides multiple buffered clock outputs, thereby reducing pin count and simplifying routing while meeting increasing reference clock needs
Solution Approach 2:
The integrated clock buffer device performs multiple functions within a single component: it receives a differential clock input, buffers the signal, and provides multiple buffered clock outputs to different destinations. This multi-functional approach eliminates the need for separate buffer components for each clock output, directly addressing the contradiction by reducing the number of pins and routing complexity while maintaining the required number of reference clock entries
3Ease of manufacture
If conventional clock distribution techniques are used, then implementation is simpler, but performance risks increase due to clock drift
Solution Approach 1:
The patent employs phase-locked loops (PLLs) within the integrated clock buffer that use feedback mechanisms to maintain precise clock signal timing and frequency. The PLLs continuously monitor and adjust the buffered clock outputs to match the reference differential clock input, thereby eliminating clock drift and ensuring high signal stability while maintaining implementation simplicity through the integrated design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FICDB effectively addresses the impracticality of increasing pin count and routing complexity by providing a robust, controlled reference clock solution with reduced drift, supporting high-speed I/O links and bandwidth requirements.
Implementation Method 1
In one embodiment, PLL phase locked loop output differential buffers (that can have individual output enabling control)
Data Source
AI summary
Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.