Differential Signal Clock Recovery Without Overhead

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Solution Overview

Problem

Existing data speed tracking methods face limitations in transmission speed, complexity, area, power consumption, and DC balance due to overhead and the need for transition information in clock recovery processes.

Innovation Solution

A data speed tracking apparatus and system that converts parallel input data into first and second signals, where identical bit values trigger transition information, reducing overhead by serializing and transmitting these signals, and using a differential output driver to prevent noise and simplify clock recovery at the receiving end.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If clock is sent at regular intervals instead of data, then data transmission speed can be found easily, but transmission speed is limited due to overhead

Engineering Contradiction:
Improvedata speed detection accuracyVSAvoiddata transmission speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts clock information from the data stream itself by detecting transitions in the differential signals, rather than sending separate clock signals. This removes the overhead of dedicated clock transmission while maintaining the ability to recover clock timing at the receiver end through transition detection in the data signals.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The differential signal pairs serve multiple functions simultaneously: they carry data information and encode clock timing information through transitions. This multi-functionality eliminates the need for separate clock channels while maintaining both data transmission and clock recovery capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If 8B10B encoding is used to add transition information, then clock recovery is enabled, but overhead increases and circuit area and power consumption increase

Engineering Contradiction:
Improveclock recovery capabilityVSAvoidcircuit area and power consumption
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation by using differential signal pairs where transitions themselves encode timing information. Instead of adding overhead bits through encoding schemes like 8B10B, the system modifies the signal domain to inherently contain clock recovery information through edge transitions, reducing computational complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The data signals themselves provide the clock recovery information through their transitions, making the system self-sufficient. The received differential signals automatically contain the timing information needed for clock recovery, eliminating the need for complex external clock synchronization circuits.

Inventive Principle:
Principle #25Self-service

3Extent of automation

If transition information is added for clock recovery, then data speed tracking is enabled, but DC balance and circuit complexity are affected

Engineering Contradiction:
Improveautomatic data speed trackingVSAvoidcircuit complexity and DC balance management
Core Design Contradiction:
Extent of automationVSDevice complexity

Solution Approach 1:

The patent uses differential signal pairs as intermediaries that naturally provide transition information for clock recovery. The differential nature of the signals serves as a mediator that encodes timing information without requiring additional DC balance management circuits, as the transitions in differential pairs inherently provide the needed timing cues.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9264155B2Apparatus and system for tracking data speed automatically
Publication Date: 2016.02.16 KOREA UNIV RES & BUSINESS FOUND
  • US9264155B2 patent drawing
  • US9264155B2 patent drawing
  • US9264155B2 patent drawing

AI summary

An apparatus and a system for automatically tracking data speed are disclosed. An embodiment of the invention provides a transmitting apparatus for automatically tracking data speed that includes: an encoder configured to convert parallelized input data according to a preset signal rule into a first signal and a second signal, where the input data is inputted as a unit of n bits, the encoder outputs the first signal and the second signal such that, if the input data includes identical bit values consecutively, one of the first signal and the second signal is converted to include transition information instead of following a differential rule with respect to the other signal; a serializer configured to serialize the first signal and the second signal; and a transmitting part configured to transmit the serialized first signal and second signal.