Differential Clock Doubler With Duty Cycle Feedback
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in generating high-frequency clock signals efficiently, as high-frequency clock signals have low amplitudes, requiring improved transmission and reception circuits, and existing clock doublers may not adequately address this need.
Innovation Solution
A clock doubler system comprising differential gates and an output buffer that adjusts duty cycles of clock signals using bias control signals, generating output clock signals with twice the frequency of input signals through phase interpolation and differential operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of clock signals is increased to improve data communication speeds, then data communication speed is improved, but the amplitude of clock signals decreases making transmission and reception more difficult
Solution Approach 1:
The patent changes the frequency parameter of the clock signal by using a clock doubler circuit that multiplies the input clock frequency by two to generate a higher frequency output clock signal. This allows data communication speed to be improved while the clock signal is generated internally at the required higher frequency, avoiding transmission issues
Solution Approach 2:
The patent segments the clock signal generation function by separating the clock doubler circuit from the main system bus transmission path. The clock doubler generates high-frequency clock signals locally within the semiconductor apparatus, so these signals do not need to be transmitted through the system bus, thus avoiding the amplitude degradation problem
2Reliability
If improved transmission circuits and reception circuits are used to transmit high-frequency clock signals through the system bus, then clock signal transmission is improved, but device complexity increases
Solution Approach 1:
The patent extracts the high-frequency clock signal generation function from the main system bus transmission path by implementing a dedicated clock doubler circuit. This separates the clock generation function from the data transmission function, so high-frequency clock signals are generated locally and do not need to be transmitted through the system bus, thereby avoiding the need for complex improved transmission and reception circuits
3Device complexity
If a clock doubler is used to generate high-frequency clock signals internally, then the burden on system bus transmission is reduced, but duty cycle distortion may occur
Solution Approach 1:
The patent implements a feedback mechanism where a duty cycle detection circuit monitors the output clock signal and generates a duty cycle control signal based on the detected duty cycle. This feedback signal is used to adjust the operation of the clock doubler circuit, thereby correcting duty cycle distortion and maintaining accurate duty cycle in the generated high-frequency clock signal
Data Source
AI summary
A clock doubler includes a first differential gate and a second differential gate. The first differential gate generates an output clock signal from a first clock signal, a first complementary clock signal, a second clock signal, and a second complementary clock signal and adjusts a duty cycle of the output clock signal based on a first bias control signal. The second differential gate generates a complementary output clock signal from the first clock signal, the first complementary clock signal, the second clock signal, and the second complementary clock signal and adjusts a duty cycle of the complementary output clock signal based on a second bias control signal.