Differential Clock Doubling for Low-Power High-Frequency Distribution
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Solution Overview
Problem
Current clock generation circuits for high-speed digital signal processing in optical transceivers face challenges in generating spectrally pure high-frequency clocks due to limitations in semiconductor technologies, resulting in complex, inefficient, and power-hungry designs.
Innovation Solution
The implementation of a low power frequency clock generation and distribution circuit using differential frequency doublers with squarer and converter circuits, integrated with phase-locked loops, to generate and distribute differential clocks, reducing power consumption and complexity by operating at lower frequencies and eliminating the need for quadrature clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct generation techniques are used for high frequency clocks, then clock frequency is improved, but spectral purity deteriorates and device complexity increases
Solution Approach 1:
The clock generation process is segmented into multiple stages: a low-frequency PLL generates a base clock, which then passes through a frequency doubler to achieve the final high-frequency output. This segmentation allows each stage to operate within its optimal frequency range, maintaining spectral purity while achieving high final frequency.
Solution Approach 2:
The system performs preliminary clock generation at a lower frequency using a PLL before applying frequency multiplication. This preliminary action at lower frequencies where semiconductor technology excels ensures spectral purity is established before the frequency doubling operation.
2Speed
If direct generation techniques are used for high frequency clocks, then clock frequency is improved, but device complexity and power consumption increase
Solution Approach 1:
The clock generation function is segmented between a PLL circuit and a frequency doubler circuit, allowing each to be optimized independently. The PLL handles low-frequency generation with high precision, while the frequency doubler handles the multiplication function, reducing overall system complexity compared to a single direct-generation circuit.
Solution Approach 2:
The frequency doubler is integrated within the data processing channel and utilizes existing circuit resources to perform frequency multiplication, eliminating the need for separate dedicated high-frequency generation circuits and reducing overall device complexity.
3Speed
If direct generation techniques are used for high frequency clocks, then clock frequency is improved, but power consumption increases
Solution Approach 1:
The power-consuming frequency multiplication function is segmented into a dedicated frequency doubler stage that operates efficiently at its optimized frequency, rather than requiring the entire system to operate at high frequency. The PLL operates at lower frequencies consuming less power, and only the necessary frequency doubling operation consumes high power.
Solution Approach 2:
The frequency multiplication function is extracted as a separate frequency doubler stage from the main PLL circuit, allowing independent optimization of each block's power consumption characteristics.
4Speed
If quadrature clocks are used for frequency multiplication, then frequency multiplication is achieved, but device complexity and power consumption increase
Solution Approach 1:
The frequency doubling function is extracted as a standalone frequency doubler circuit that directly processes the PLL output without requiring quadrature clock generation. This eliminates the complex quadrature signal generation and mixing circuits while achieving the same frequency multiplication effect.
Solution Approach 2:
The frequency doubler uses a simplified circuit topology that copies and transforms the input clock signal through nonlinear elements to generate the doubled frequency, avoiding the need for complex quadrature signal paths.
Data Source
AI summary
Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.