Differential Clock Driver for Pinless DRAM Low-Power Mode
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Solution Overview
Problem
Semiconductor memories, particularly volatile memories like DRAM, face increased power consumption when in a clock interruption mode due to the lack of a separate pin for recognizing this mode, leading to inefficient power usage.
Innovation Solution
A clock driver generates a chip enable signal using a differential clock signal pair to transition between operational and interruption modes without an additional pin, utilizing a differential buffer and signal coupler to output a chip enable signal based on differential internal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a clock buffer without a separate pin is used to recognize clock interruption mode, then device complexity is reduced, but power consumption increases due to inability to enter low power mode
Solution Approach 1:
The clock buffer is designed to perform multiple functions: it buffers the clock signal during normal operation and simultaneously detects clock interruption mode by monitoring the clock signal characteristics. This eliminates the need for a separate detection pin while enabling low power mode entry, thus resolving the contradiction between reduced device complexity and power consumption management.
Solution Approach 2:
The clock buffer uses its own internal circuitry to detect the clock interruption mode by monitoring the clock signal it receives. The buffer's internal nodes naturally exhibit different voltage levels during clock interruption versus normal operation, allowing the system to self-detect the mode without external assistance, thereby maintaining low power capability while simplifying the pin structure.
2Use of energy by moving object
If a separate pin is added for chip enable signal input, then power consumption control is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The clock signal serves dual purposes: it provides the clock function during normal operation and simultaneously acts as the chip enable signal during interruption mode. By making the clock signal multi-functional, the invention eliminates the need for a separate chip enable pin while maintaining the ability to control power consumption effectively.
Solution Approach 2:
The invention merges the clock signal function and chip enable signal function into a single signal line. The clock buffer's output is directly used to generate the chip enable signal, combining what would traditionally be separate functions into one integrated pathway, thereby reducing pin count while preserving power management capability.
3Ease of manufacture
If the clock signal is used to generate chip enable signal without additional pins, then manufacturing cost is reduced, but signal integrity may be compromised
Solution Approach 1:
The clock buffer's output signal is segmented into different functional paths: one path provides the buffered clock signal to the memory chip, while another path derives the chip enable signal. This segmentation allows the same physical signal to be processed differently for different purposes, maintaining signal integrity for both functions while using a single pin.
Solution Approach 2:
The clock buffer acts as an intermediary that processes the incoming clock signal and generates both the buffered clock output and the chip enable signal. This intermediary processing ensures that the original clock signal's integrity is preserved for timing operations while a derived version is used for enable control, maintaining reliability for both functions.
Data Source
AI summary
The present disclosure provides a clock driver, an operating method thereof, a memory device including the clock driver, and a memory system. A clock driver according to an embodiment includes a differential buffer configured to output a differential amplified clock signal pair based on a differential external clock signal pair, and a signal coupler configured to generate a differential internal clock signal pair based on the differential amplified clock signal pair, and output a chip enable signal to the memory chip based on the differential internal clock signal pair.