Integrated Differential Clock Buffering for Multi-Reference PLL Distribution
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Solution Overview
Problem
As integrated circuits become more complex and require more reference clock signals, the number of pins and routing complexity for differential clock signals increase, making existing clock distribution techniques impractical.
Innovation Solution
A fully integrated clock differential buffer (FICDB) is used to provide a robust reference clock signal to high-speed interconnects and processing cores, reducing performance risks by controlling reference clock drift and jitter, and allowing multiple reference clock pairs to be distributed efficiently within a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional external clock signals are provided to meet increasing reference clock needs, then the number of reference clock signals increases, but the number of pins and routing complexity increases making the solution impractical
Solution Approach 1:
The patent merges multiple clock buffer functions into a single integrated clock buffer device. Instead of using separate external clock buffers for each clock signal, the invention integrates multiple differential clock signal buffering capabilities within one chip, reducing the number of external components and simplifying routing while maintaining the ability to provide multiple reference clock signals to different destinations
Solution Approach 2:
The integrated clock buffer is designed to perform multiple functions: it can buffer multiple differential clock signals simultaneously, provide different clock outputs to different destinations, and support various clock distribution topologies. This multi-functional design allows a single device to replace what would traditionally require multiple separate clock buffer components
2Reliability
If differential clock signals are used with increasing reference clock needs, then clock signal quality is maintained, but the number of pins increases making the solution impractical
Solution Approach 1:
The patent combines multiple differential clock signal paths within a single integrated device, allowing multiple high-quality differential clock outputs to be generated from a single package. This eliminates the need for multiple external clock buffer components, thereby reducing pin count while maintaining differential signal quality through controlled impedance routing and proper signal termination within the integrated device
Data Source
AI summary
Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.