Differential Clock Sampling Circuit With Retimed Precharge Accuracy
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Solution Overview
Problem
Existing duty cycle and phase placement sampling circuits have limited accuracy and are unable to effectively sample differential CML clock signals, leading to errors in duty cycle and phase placement, particularly at high data rates and with small duty cycle variations.
Innovation Solution
A duty cycle and phase placement sampling circuit with a precharge retiming circuit and replicated differential pair stages, allowing for accurate sampling of differential inputs and eliminating initial errors by ensuring synchronized de-assertion of precharge signals, enabling precise duty cycle and phase placement measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a typical prior art sampling circuit is used, then the circuit can sample duty cycle and phase placement, but the accuracy is limited and initial errors cannot be eliminated
Solution Approach 1:
The patent applies preliminary action by de-asserting the precharge signal at a precisely controlled time point before the clock transitions. This timing control ensures that both differential branches start their integration from an equal voltage state, eliminating initial errors that would otherwise compromise measurement accuracy. The precharge retiming circuit specifically implements this by generating a precharge de-assertion signal that occurs at a predetermined time point prior to clock edge transitions.
Solution Approach 2:
The patent employs feedback mechanisms through the precharge retiming circuit that monitors clock signal transitions and adjusts the precharge de-assertion timing accordingly. This feedback ensures that the precharge is always de-asserted at the correct relative time point before clock transitions, maintaining measurement accuracy across varying operating conditions and eliminating initial voltage mismatches between differential branches.
2Productivity
If the precharge signal is de-asserted at the wrong time, then the circuit operates, but large initial errors occur that cannot be overcome by duty cycle errors
Solution Approach 1:
The precharge retiming circuit performs preliminary action by precisely timing the precharge de-assertion to occur at a predetermined time point before clock transitions. This ensures that integration begins from equal voltage states in both differential branches, preventing large initial errors that would otherwise render the sampling operation ineffective for measuring small duty cycle variations.
Solution Approach 2:
The patent applies preliminary anti-action by proactively controlling the precharge de-assertion timing to prevent initial voltage mismatches before they can occur. The precharge retiming circuit anticipates clock transitions and adjusts the precharge release timing accordingly, counteracting potential errors before they affect the measurement of output voltage differences.
3Speed
If high data rates are used, then the operating speed increases, but the timing margins decrease making accurate sampling more difficult
Solution Approach 1:
The precharge retiming circuit performs preliminary action by de-asserting the precharge signal at a predetermined time point before clock transitions occur. This advance timing control ensures that integration starts from equal voltage states regardless of how fast the clock transitions occur, maintaining measurement precision even at high data rates where timing margins are compressed.
Solution Approach 2:
The patent implements dynamics by making the precharge de-assertion timing dynamically synchronized with clock transitions through the precharge retiming circuit. This dynamic adjustment ensures that the predetermined time point offset is maintained relative to moving clock edges, allowing accurate sampling to continue even as operating speeds increase and timing margins decrease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high accuracy in duty cycle and phase placement sampling, resolving small duty cycle variations and enabling precise control, with improved worst-case resolution and capability to handle differential CML signals, as demonstrated by SPICE simulations showing minimal error and accurate output node voltage differences.
Implementation Method 1
The circuit also includes two sets of feedback transistors, one set for each differential branch. The NMOS transistor 15 and PMOS transistor 55 are cross-connected to the output node OUT 40 in the other differential branch. Likewise, NMOS transistor 20 and PMOS transistor 60 are similarly cross-connected to OUT* 35.
Implementation Method 2
A differential current mode clock signal is applied to the inputs CLK and CLK*. The precharge signal is then de-asserted which, in combination with NMOS transistors 15 and 20, provides a path for current to travel to ground. As the input signals CLK and CLK* switch, NMOS transistors 25 and 30 alternately turn ON and OFF thereby charging the integrating capacitors 65 and 70.
Data Source
AI summary
A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.