Differential Clock Generation With Quadrature Doubling for Low Jitter
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Solution Overview
Problem
Current semiconductor technologies face challenges in generating spectrally pure high-frequency clocks for optical transceivers due to complex circuitry, poor performance, and high power consumption, especially at high data rates where conventional techniques result in increased jitter and phase noise.
Innovation Solution
A high frequency clock generation circuit that includes a phase frequency detector, a controlled oscillator, a quadrature clock generation circuit, and a frequency doubler, which generates fully differential and balanced clocks by comparing differential reference and feedback clocks, and actively controls quadrature phase deviation using an injection locked quadrature ring oscillator and active feedback loop to reduce jitter and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct generation techniques are used for high frequency clock generation, then the clock frequency can be achieved, but the circuit complexity increases and spectral purity deteriorates
Solution Approach 1:
The patent segments the clock generation process into multiple stages: a first PLL generates an intermediate frequency clock, which is then divided and processed through additional PLLs to achieve the final high frequency. This multi-stage approach reduces the complexity of each individual stage while maintaining the ability to generate high frequency clocks with good spectral purity.
Solution Approach 2:
The patent employs nested PLL structures where multiple phase-locked loops are hierarchically arranged. The output of one PLL serves as the input reference for another PLL, creating a nested configuration that enables progressive frequency multiplication while maintaining control over phase noise and spectral purity at each stage.
2Speed
If direct generation techniques are used for high frequency clock generation, then the clock frequency can be achieved, but the spectral purity deteriorates due to increased jitter and phase noise
Solution Approach 1:
By dividing the frequency multiplication into multiple smaller steps through different PLL stages, each stage operates within a manageable frequency range where phase noise and jitter can be better controlled, resulting in improved spectral purity of the final high frequency clock.
Solution Approach 2:
The patent utilizes feedback mechanisms within each PLL stage to continuously monitor and correct phase deviations. The feedback loops filter out noise and jitter, ensuring that each intermediate clock signal maintains high spectral purity before being passed to the next frequency multiplication stage.
3Device complexity
If conventional clock generation circuits are used, then the design is simpler, but the power consumption increases at high data rates
Solution Approach 1:
The patent employs dynamic frequency planning where different PLL stages are activated based on the required output frequency. This allows the system to use only the necessary circuitry for the current operating condition, reducing power consumption compared to always operating a single high-frequency generator at full power.
Data Source
AI summary
Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.