Differential Clock Transfer Over One Wire Using a Stable Carrier
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Solution Overview
Problem
Existing solutions for transferring frequency/phase/time information between two independent clock domains over a single physical wire are prone to performance degradation due to carrier instability and frequency offsets, which are not supported by current implementations like the 8A34003 system synchronizer.
Innovation Solution
A method and system that utilize a stable carrier clock signal to phase-lock client clock signals from multiple domains, encode phase changes and other information onto the carrier signal by modulating its timing, and transmit this information over a single wire, ensuring stability and compatibility with multiple clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If one physical wire is used to carry frequency/phase/time information for two independent clock domains, then the number of wires is minimized, but the system introduces carrier instability and frequency offset issues that degrade performance
Solution Approach 1:
The patent segments the clock domain information into two independent parts: a stable carrier clock domain and client clock domain information. By separating the carrier function from the client information, the system can transmit multiple clock domains over a single wire without the carrier being affected by client domain variations, thus resolving the contradiction between wire minimization and carrier stability.
Solution Approach 2:
The patent introduces a stable reference clock as an intermediary element that serves as the carrier. This intermediary provides a stable foundation for transmitting client clock domain information without being directly affected by the client domains themselves, thereby maintaining carrier stability while still enabling multi-domain transmission over a single wire.
2Device complexity
If existing PLL implementations are used to transfer clock domain information, then the system architecture is simple, but only one clock domain can be carried per physical wire
Solution Approach 1:
The patent makes the single physical wire universal by enabling it to carry information from multiple clock domains simultaneously. The wire serves multiple functions: carrying the stable carrier clock signal, transmitting client clock domain phase information, and maintaining backward compatibility with existing single-clock-domain systems, thus achieving multi-functionality without significantly increasing device complexity.
Solution Approach 2:
The patent changes the encoding parameters of the clock domain information by using phase-difference encoding relative to the carrier clock. Instead of directly transmitting absolute phase values, the system encodes phase differences, allowing multiple client clock domains to be represented on the same wire through parameter modulation without requiring complex additional hardware.
3Ease of manufacture
If the carrier clock signal is used directly from an external source, then the system is easier to implement, but the carrier may disappear, change source dynamically, or become unstable
Solution Approach 1:
The patent applies preliminary action by generating and stabilizing the carrier clock signal locally within the device before it is used to modulate client clock domain information. The carrier clock signal is generated from a stable reference and undergoes preliminary phase-locking and stabilization processes, ensuring that the carrier is already stable and reliable before being used for information transmission, thus preventing carrier disappearance or instability issues.
Solution Approach 2:
The patent implements feedback mechanisms through phase-locked loops (PLLs) that continuously monitor and adjust the carrier clock signal and client clock domain information. The feedback ensures that any deviations in the carrier signal are corrected in real-time, maintaining carrier stability and preventing dynamic source changes or signal disappearance, while still keeping the implementation relatively simple through standard PLL circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable transfer of frequency/phase/time information from multiple client clock domains over a single wire, reducing system noise and meeting requirements for next-generation networking equipment, while minimizing the number of physical wires needed.
Implementation Method 1
generating, in the first integrated circuit, the carrier clock signal from the stable reference clock source and phase locking the generated carrier clock signal to the stable reference clock source
Implementation Method 2
modulating the carrier signal to generate and send first and second phase word information and non-phase word information over a single wire
Data Source
AI summary
A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.