Differential Clock Signal Conditioning for Precise DRAM Timing Tests
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Solution Overview
Problem
Current integrated circuit testing systems face challenges in accurately simulating operating conditions due to signal propagation delays in long cables and high complexity, leading to difficulties in testing timing characteristics and high costs, especially when generating and maintaining high fidelity clock signals for DRAM devices.
Innovation Solution
A test system with an integrated test circuit mounted on the test head or load board, utilizing a clock signal conditioning system that corrects duty cycle errors and phase placement to improve phase interpolation linearity, allowing for precise timing control and reduced complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testers with long cables are used to test integrated circuits, then testing can be performed, but signal propagation delays increase and timing characteristic testing becomes difficult
Solution Approach 1:
The patent introduces an integrated test circuit as an intermediary component mounted on the load board, which generates and conditions clock signals locally. This intermediary eliminates the need for long cable connections between the tester and test head, thereby reducing signal propagation delays and improving timing characteristic testing accuracy.
Solution Approach 2:
The integrated test circuit performs preliminary actions by generating and conditioning clock signals in advance before they are used for testing. The clock signal conditioning circuit pre-adjusts duty cycle and phase parameters, ensuring accurate timing characteristics are established before the actual testing process begins.
2Reliability
If conventional testers are used to test integrated circuits, then testing functionality is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the clock signal generation and conditioning functions from the complex conventional tester system and places them in a separate integrated test circuit mounted on the load board. This extraction simplifies the main tester system while maintaining full testing functionality through the distributed architecture.
Solution Approach 2:
The integrated test circuit provides self-service by generating and conditioning its own clock signals locally without requiring complex external signal conditioning equipment. The circuit autonomously adjusts duty cycle and phase parameters, reducing the complexity of the overall testing system while maintaining functionality.
3Speed
If traditional clock signal generation is used with phase interpolators, then clock signals are generated, but duty cycle errors and phase placement inaccuracies occur
Solution Approach 1:
The patent implements feedback mechanisms in the clock signal conditioning circuit that continuously monitor and adjust duty cycle and phase parameters. The circuit receives feedback about signal characteristics and automatically corrects errors, ensuring high precision in clock signal generation while maintaining fast operation speeds.
Solution Approach 2:
The clock signal conditioning circuit dynamically changes key parameters including duty cycle, phase shift, and frequency to optimize clock signal quality. By adjusting these parameters in real-time, the system achieves both high speed operation and high precision in phase and duty cycle control.
Data Source
AI summary
A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.