Differential CMOS Wideband Clock Circuit With Low-Power Tuning
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Solution Overview
Problem
Existing wideband clock generators have high energy consumption, particularly unsuitable for mobile applications.
Innovation Solution
A CMOS-based wideband clock generator with a differential structure, utilizing cross-coupled PMOS transistors and a symmetrical varactor diode circuit, incorporates an adjustable diode block of NMOS transistors with control circuits that adjust the gate connections based on binary programming signals, reducing energy consumption by eliminating the need for decoupling capacitors and intermediate amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional wideband clock generators are used, then clock signal generation is achieved, but energy consumption is high
Solution Approach 1:
The patent extracts and eliminates unnecessary components from the conventional clock generator design. Specifically, it removes decoupling capacitors and intermediate amplifiers that are typically present in wideband clock generators, thereby reducing energy consumption while maintaining the essential clock signal generation function. This extraction of non-essential elements directly addresses the high energy consumption problem in mobile applications.
Solution Approach 2:
The patent changes key design parameters of the clock generator circuit. It modifies the oscillator design to operate efficiently without traditional decoupling capacitors, and adjusts the amplifier stage parameters to achieve proper signal conditioning with minimal energy expenditure. These parameter changes enable the circuit to maintain reliability while significantly reducing power consumption for mobile applications.
2Area of stationary object
If decoupling capacitors and intermediate amplifiers are included, then signal stability is improved, but circuit area increases
Solution Approach 1:
The patent removes decoupling capacitors and intermediate amplifiers from the circuit design. By extracting these components, the circuit area is significantly reduced while the design compensates through alternative methods to maintain signal stability, such as optimized oscillator design and direct coupling techniques that eliminate the need for traditional signal conditioning stages.
Solution Approach 2:
The patent merges functions that were previously performed by separate components. The oscillator stage is designed to directly provide stable signals without requiring separate decoupling and amplification stages. This functional merging reduces the number of discrete components and minimizes circuit area while maintaining the necessary signal stability through integrated design techniques.
3Adaptability or versatility
If traditional clock generator design is used, then broad frequency range is achieved, but energy consumption increases
Solution Approach 1:
The patent implements a dynamic design that allows the clock generator to operate across a broad frequency range while adapting its internal parameters to maintain efficiency. The oscillator circuit is designed with variable parameters that can be adjusted dynamically across different frequency bands, enabling wideband operation without the energy penalties associated with traditional fixed-design approaches. This dynamic adaptability allows the circuit to optimize its energy consumption at each operating frequency.
Solution Approach 2:
The patent employs parameter changes to achieve broad frequency coverage with low energy consumption. By designing the oscillator and amplifier stages with adjustable parameters that can be optimized for different frequency ranges, the circuit maintains versatility across wide bandwidths while consuming minimal energy. This approach replaces the energy-intensive traditional design with a parameter-optimized architecture that adapts to different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces energy requirements, allows for larger oscillator signal amplitudes, and achieves low phase noise, while also minimizing circuit area and enabling operation up to several GHz frequencies.
Implementation Method 1
a symmetrical varactor diode circuit, which has a capacitance that can be adjusted by a control voltage
Implementation Method 2
each of the NMOS transistors being assigned a control circuit which, depending on a binary programming signal, switches the respective gate terminal either to low resistance connects to the respective drain connection or to the respective source connection
Implementation Method 3
two cross-coupled PMOS transistors, each of which has a source connection, a drain connection and a gate connection
Data Source
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Figure 6
AI summary
Differential wideband clock with a voltage-controlled oscillator for generating a differential oscillator signal, comprising two cross-coupled PMOS transistors, each having a source terminal, a drain terminal, and a gate terminal, comprising a symmetrical varactor diode circuit having a capacitance adjustable by a control voltage and acting between the two drain terminals, comprising an inductor circuit connected in parallel to the varactor diode circuit, having a center tap, and comprising two output terminals for tapping the differential oscillator signal, each connected to one of the drain terminals, with a positive supply contact and a negative supply contact, and with a quiescent current source for supplying the oscillator with a quiescent current.the first pole of which is connected to the positive supply contact and the second pole of which is connected to the source terminals of the PMOS transistors, wherein an adjustable diode block is provided which comprises a plurality of NMOS transistors, each having a source terminal, a drain terminal and a gate terminal, wherein their drain terminals are connected to the center tap of the inductor circuit and their source terminals are connected to the single negative supply contact, wherein each of the NMOS transistors is associated with a control circuit which, depending on a binary programming signal, connects the respective gate terminal either to the respective drain terminal or to the respective source terminal.