Differential Column ADC Noise Rejection in CMOS Image Sensors
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Solution Overview
Problem
High-resolution CMOS image sensors face challenges with row-wise and column-wise noise, which limit their sensitivity and introduce undesirable artifacts, particularly due to power supply noise and column fixed-pattern noise, in achieving high dynamic range and low power consumption.
Innovation Solution
The implementation of differential input, single-slope, column-parallel analog-to-digital converter (ADC) architectures that differentially drive a comparator stage using pixel and ramp signals, reducing power supply noise and enhancing noise rejection through differential sampling and crossover detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If single-slope column-parallel ADC architecture is used, then power consumption is reduced and dynamic range is improved, but noise (row-wise and column-wise) limits sensitivity
Solution Approach 1:
The patent changes the operational parameters of the ADC by implementing dual-slope integration instead of single-slope conversion. This involves integrating the pixel signal over a first time period and the reference signal over a second time period, then comparing the accumulated voltages. This parameter change from single-slope to dual-slope operation improves noise rejection while maintaining low power consumption characteristics of the column-parallel architecture.
Solution Approach 2:
The patent implements feedback mechanisms where the ADC controller monitors the conversion process and adjusts timing parameters based on the integration results. The dual-slope integration process inherently provides feedback by comparing the accumulated pixel signal voltage with the accumulated reference signal voltage, enabling automatic noise cancellation and improving sensitivity without increasing power consumption.
2Measurement precision
If resolution is increased, then dynamic range is improved, but noise artifacts and sensitivity limitations worsen
Solution Approach 1:
The patent converts the harmful effect of noise into a beneficial outcome by using dual-slope integration. The first integration of the pixel signal and the second integration of the reference signal are designed such that noise components accumulated during the first period are subtracted during the second period. This transforms noise from a harmful artifact into a cancelable component, improving measurement precision while maintaining high resolution capability.
Solution Approach 2:
The patent performs preliminary integration of the pixel signal over a first time period before the actual conversion process. This preliminary action accumulates the signal and associated noise, which is then used as a reference for noise cancellation during the second integration period. By performing this preliminary integration in advance, the system prepares noise cancellation data that improves measurement precision without adding noise artifacts to the final output.
3Measurement precision
If column-parallel ADC architecture is used, then read noise is reduced and dynamic range is improved, but column fixed-pattern noise (CFPN) persists
Solution Approach 1:
The patent segments the ADC operation into distinct phases: pixel signal integration phase and reference signal integration phase. By separating these operations into different time periods with different integration paths, the system can process pixel signals through one channel and reference signals through another channel, then compare the results. This segmentation allows independent optimization of each path and enables cancellation of column fixed-pattern noise that affects both paths similarly.
Solution Approach 2:
The patent introduces the reference signal integration as an intermediary process that mediates between the pixel signal and the final conversion result. The reference signal, integrated over a second time period, serves as a mediator that captures column fixed-pattern noise and other systematic errors. By comparing the pixel signal integration result with the reference signal integration result, the system can eliminate the intermediary's introduced errors, thereby removing column fixed-pattern noise while preserving the low read noise advantage.
Data Source
AI summary
Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.