Differential Comparator Circuit for Low-Power PAM4 Data Restoration

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Solution Overview

Problem

In semiconductor integrated circuits with differential configurations, restoring data with low power consumption is challenging due to high power consumption and processing load associated with increasing numbers of comparators needed for multi-value amplitude modulation methods like PAM4, which affects power efficiency.

Innovation Solution

The semiconductor integrated circuit configures a sampler using a reduced number of comparators, specifically a comparator for polarity determination and one for amplitude absolute value determination, reducing the number of comparators and associated power consumption by using differential input and output type comparators and differential amplifiers for reference voltage generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-value amplitude modulation methods like PAM4 are used, then data transmission capability is improved, but power consumption and processing load increase due to requiring more comparators

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data restoration function into two independent comparators: one dedicated to polarity determination and another to amplitude absolute value determination. This segmentation allows each comparator to operate independently and efficiently, avoiding the need for multiple comparators that would be required in conventional PAM4 decoding approaches, thereby reducing power consumption while maintaining high data transmission capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements universal comparator circuits that can handle multiple functions. The first comparator determines both polarity and amplitude information, while the second comparator handles amplitude absolute value determination. These comparators serve multiple purposes in the data restoration process, eliminating the need for separate dedicated circuits for each function and reducing overall power consumption

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If the number of comparators is increased to support multi-value amplitude modulation, then data restoration accuracy is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvedata restoration accuracyVSAvoidnumber of comparators
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the data restoration task into two precise measurement functions handled by separate comparators: polarity detection and amplitude absolute value detection. This segmentation achieves high measurement precision for each function while avoiding the complexity of using multiple comparators in a conventional multi-level decoding architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the measurement parameters by using differential input and output type comparators that operate on voltage difference rather than absolute voltage levels. This parameter change enables accurate data restoration with fewer comparators, as the differential approach inherently provides noise immunity and improved measurement precision without requiring additional comparator stages

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10666466B2Semiconductor integrated circuit, receiving device, and communication system
Publication Date: 2020.05.26 KIOXIA CORP
  • US10666466B2 patent drawing
  • US10666466B2 patent drawing
  • US10666466B2 patent drawing

AI summary

A semiconductor integrated circuit includes a pair of differential signal lines including first and second signal lines, a first comparator, and a second comparator. The first comparator is configured to output at least one of a first signal corresponding to a difference between a potential of a first input node and a potential of a second input node, and a second signal corresponding to a difference between a potential of a third input node and a potential of a fourth input node. The second comparator is configured to output at least one of a third signal corresponding to a difference between a potential of a fifth input node and a potential of a seventh input node, and a fourth signal corresponding to a difference between a potential of a sixth input node and a potential of a eighth input node.