Mixed-Signal Differential Current Circuit for Compact Edge AI Inference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional digital circuitry for neural network models is large, energy-intensive, and causes latency issues when deployed in edge devices due to the need for significant memory and compute resources, making them unsuitable for real-time inference and energy-efficient operation in edge computing environments.
Innovation Solution
The implementation of a mixed-signal integrated circuit with a binary-weighted global reference signal source, local differential current circuits, and a common-mode control circuit that adjusts differential current between summation nodes, allowing for efficient weighted sum computations using analog signals and reducing the need for large digital memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional digital circuitry is used for neural network computations, then computing accuracy is maintained, but circuit area and energy consumption increase significantly
Solution Approach 1:
The patent replaces traditional digital circuitry with a mixed-signal architecture that uses analog circuits for weighted sum computations. Specifically, current-mode analog circuits perform multiply-accumulate operations natively, eliminating the need for digital multipliers and accumulators. This substitution of analog for digital mechanisms in the computational path significantly reduces circuit area while maintaining computing accuracy through careful design of the analog-to-digital conversion interface.
2Measurement precision
If traditional digital circuitry with large memory is used, then neural network model accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent substitutes digital memory access operations with analog weight storage in current sources. Weights are represented as current amplitudes in analog circuits, allowing direct participation in computations without digital memory access. This eliminates the energy cost of reading weights from digital memory and processing them through digital multipliers, significantly reducing energy consumption while preserving neural network model accuracy.
Solution Approach 2:
The patent performs weight initialization and configuration in advance during device fabrication or system setup. Weight values are programmed into the analog current sources before operation, eliminating the need for continuous digital memory access during inference. This preliminary action of pre-configuring the analog circuit parameters reduces runtime energy consumption while maintaining model accuracy.
3Power
If remote computing systems are used for neural network inference, then compute power is sufficient, but latency increases due to network transmission
Solution Approach 1:
The patent segments the neural network computation into analog processing operations performed locally at the edge device. By implementing a dedicated mixed-signal accelerator on-chip, the system performs weighted sum computations locally without transmitting data to remote servers. This segmentation of computation from centralized cloud processing eliminates network transmission latency while maintaining sufficient compute power through specialized analog circuitry.
4Use of energy by moving object
If analog signal processing is used for weighted sum computations, then energy efficiency improves, but circuit complexity increases
Solution Approach 1:
The patent merges multiple functions into unified analog circuit blocks. Current-mode analog circuits simultaneously perform multiplication (through current mirroring and scaling) and accumulation (through current summation at nodes) in a single hardware structure. This merging of multiply and accumulate operations into unified analog computational units reduces the number of separate circuit components needed, thereby reducing overall circuit complexity while maintaining energy efficiency.
Solution Approach 2:
The patent designs universal analog computational units that can perform different neural network operations. The same current-mode analog circuitry handles weighted sums, bias additions, and activation function approximations through configurable current ratios and feedback mechanisms. This multi-functionality reduces the need for specialized circuit blocks for each operation, simplifying the overall circuit architecture while preserving energy efficiency.
Data Source
AI summary
A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.