Differential Current Sensing Circuit for High-Resolution Low-Power ADCs
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Solution Overview
Problem
Prior art analog to digital converters (ADCs) are power consumptive, provide low resolution, and are not suitable for applications with limited power budgets or high performance requirements due to inadequate resolution and accuracy.
Innovation Solution
The development of novel ADC designs and architectures that enable high-resolution digital format data conversion with simultaneous drive and sense capabilities, utilizing a single line for both power provision and signal sensing, and incorporating non-linear N-bit digital to analog converters (DACs) to achieve broad dynamic range and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art ADC designs are used, then power consumption is high, but resolution and measurement precision are insufficient
Solution Approach 1:
The ADC is divided into multiple parallel sub-ADCs (e.g., four 2-bit sub-ADCs) that simultaneously process different segments of the input signal range. Each sub-ADC operates at lower resolution but together they achieve high overall resolution through parallel operation, reducing power consumption compared to a single high-resolution ADC
Solution Approach 2:
The system dynamically selects which sub-ADCs are active based on the input signal amplitude. For small signals, only a subset of sub-ADCs operates, reducing power consumption. The selection logic dynamically adjusts the active sub-ADC configuration to match the signal level, achieving variable resolution and power trade-offs
2Measurement precision
If high resolution ADCs are designed, then measurement precision improves, but device complexity increases
Solution Approach 1:
The high-resolution conversion task is segmented across multiple low-resolution sub-ADCs. Instead of implementing one complex high-resolution ADC, the system uses several simple sub-ADCs working in parallel, each handling a portion of the dynamic range, thereby reducing individual circuit complexity while achieving high overall resolution
Solution Approach 2:
Multiple low-resolution conversion results are merged through a combination logic circuit to produce the final high-resolution digital output. The merging process integrates the outputs from parallel sub-ADCs along with the dynamic selection signal to reconstruct the full-resolution representation of the input analog signal
3Measurement precision
If multiple lines are used for drive and sense, then signal accuracy improves, but device complexity and power consumption increase
Solution Approach 1:
The same physical line serves dual functions: it acts as both the drive line (providing current to the sensor) and the sense line (carrying the sensor output signal back to the ADC). This multi-functional use of a single line eliminates the need for separate drive and sense paths, reducing circuit complexity while maintaining measurement capability through careful signal differentiation in the digital domain
Data Source
AI summary
A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.