Differential DAC Capacitor Array for Low-Power SAR ADC Conversion
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Solution Overview
Problem
SAR analog-to-digital converters face challenges in reducing power consumption while maintaining conversion precision, especially in small-sized and low-power devices like mobile devices and wireless sensors, due to high energy consumption during capacitor switching and voltage dynamic range requirements.
Innovation Solution
The implementation of a DAC capacitor array with a primary switch and multiplexers, where capacitors are arranged in a specific capacitance ratio and used in a differential configuration to narrow the voltage variation range, reducing power consumption by optimizing the conversion process and capacitor array requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitor switching is performed in conventional SAR ADC, then conversion precision is achieved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by dividing the conversion process into distinct phases (sampling phase and conversion phase) with periodic switching of capacitor arrays. The first and second capacitor arrays are alternately connected to the comparator input during conversion phases, reducing frequent switching operations while maintaining precision through systematic charge redistribution.
Solution Approach 2:
The patent segments the capacitor array into multiple independent groups (first capacitor array and second capacitor array) that can be operated separately. This segmentation allows selective activation of capacitor groups during different conversion phases, reducing the total number of switching operations required compared to a single monolithic capacitor array.
2Measurement precision
If voltage dynamic range is increased for precise conversion, then conversion precision improves, but power consumption increases
Solution Approach 1:
The patent applies equipotentiality by connecting both the first and second capacitor arrays to the same reference voltage (Vref/2) at their common terminals. This creates a balanced differential configuration where the voltage swing is minimized around a common reference potential, reducing the overall voltage dynamic range required while maintaining conversion precision through differential comparison.
3Volume of moving object
If capacitor array size is reduced for small device integration, then device size decreases, but conversion precision deteriorates
Solution Approach 1:
The patent segments the capacitor array into multiple smaller groups (first and second capacitor arrays) that can be independently controlled. This segmentation allows the total capacitance to be distributed across smaller physical units, reducing the area required for each capacitor group while maintaining the overall precision through coordinated operation of multiple groups during conversion phases.
Data Source
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AI summary
The present invention relates to the field of integrated circuits, and relate to a DAC capacitor array, an SAR analog-to-digital converter and a method for reducing power consumption thereof. The method includes: connecting one terminal of each capacitor in a first capacitor array and a second capacitor array to a first reference voltage via a corresponding primary switch, and connecting the other terminal of each capacitor in the first capacitor array and the second capacitor array to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor in the first capacitor array and the second capacitor array according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by further comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array. According to the embodiments of the present invention, conversion power consumption may be reduced.