Differential DAC Architecture With Clamp Transistors for Smaller Chips
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Solution Overview
Problem
Existing digital-to-analog converters face challenges in reducing chip size and manufacturing cost while maintaining high voltage levels, especially when dealing with large numbers of divided voltage levels.
Innovation Solution
The digital-to-analog converter employs a differential amplifier with multiple differential pairs connected in parallel, using low voltage current sources and clamp transistors to generate tail currents, thereby reducing area without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of reference voltages is increased to increase the number of gradations, then the number of colors and brightness levels can be increased, but the wiring area and number of switch elements in the decoder increase, leading to increased chip size and manufacturing cost
Solution Approach 1:
The patent divides the reference voltage selection into multiple stages. Instead of directly selecting from all reference voltages, the decoder first selects from a smaller set of candidate reference voltages, then further refines the selection. This segmentation reduces the number of switch elements needed at each stage while achieving the same total number of gradations.
Solution Approach 2:
The patent introduces a two-dimensional selection process: first selecting from multiple candidate reference voltage groups, then selecting specific reference voltages within each group. This dimensional approach allows the system to achieve high gradation counts without requiring a single large-scale decoder, thereby reducing chip area.
2Quantity of substance
If the number of reference voltages is increased to increase the number of gradations, then the number of colors and brightness levels can be increased, but the wiring area and number of switch elements in the decoder increase, leading to increased manufacturing cost
Solution Approach 1:
The patent segments the reference voltage generation and selection process into multiple stages with intermediate selection steps. This reduces the complexity of the decoder circuit, decreasing the number of switch elements and wiring required, which directly lowers manufacturing cost while maintaining high gradation capability.
Solution Approach 2:
The patent merges the functions of multiple decoders into a hierarchical structure where a first decoder and second decoder work together. This consolidation reduces the total number of switch elements compared to using separate full-scale decoders, thereby reducing manufacturing cost.
3Adaptability or versatility
If multiple differential pairs are used to handle large numbers of divided voltage levels, then the conversion capability is improved, but the area occupied by the differential amplifier increases
Solution Approach 1:
The patent segments the differential amplification process into multiple stages corresponding to the hierarchical decoder structure. Each stage handles a subset of the voltage levels, allowing the use of fewer differential pairs at each stage while collectively covering all required gradations. This reduces the total area compared to using a single large-scale differential amplifier.
Solution Approach 2:
The patent introduces a multi-stage amplification architecture where different differential pairs operate at different stages of the conversion process. This dimensional approach to amplification allows the system to achieve high conversion capability with a distributed arrangement of smaller differential amplifiers rather than one large amplifier, reducing total area.
Data Source
AI summary
The disclosure includes: a decoder generating multiple input voltages each having one or the other of two reference voltages selected from multiple reference voltages, using a high voltage digital data signal obtained by increasing the amplitude of a low voltage digital data signal; and a differential amplifier including multiple differential pairs and receiving the input voltages at the non-inverting input terminals of the differential pairs and receiving an output voltage signal at the inverting input terminals to generate an output voltage signal having one of the voltage levels obtained by dividing the two reference voltages into a power of 2. The differential amplifier includes: multiple current sources generating tail currents flowing through the tails of the differential pairs; and multiple clamp transistors provided respectively between the tails of the differential pairs and the current sources and holding a voltage applied to each current source at or below a low voltage.