Differential ΔΣ DAC Element Matching Without DC Offset Noise
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Solution Overview
Problem
Conventional delta-sigma digital-to-analog converters (DACs) suffer from code-dependent errors and noise distortion due to mismatches among DAC elements, leading to inefficiencies in power and area usage, as well as increased thermal noise, especially in high-performance systems.
Innovation Solution
A method for dynamically selecting circuit elements using multiple selector signals for dynamic element matching (DEM) that eliminates the need for separate DC offset circuitry, allowing for true differential-output configurations with first-order mismatch noise shaping, reducing thermal noise and improving power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DWA algorithm is used to provide first-order mismatch noise shaping, then code-dependent errors are whitened and noise is moved beyond the signal band, but a DC offset must be added which injects unnecessary noise and wastes power
Solution Approach 1:
The patent extracts and eliminates the DC offset addition step from the conventional DWA algorithm implementation. By using a modified element rotation algorithm that can directly handle signed input codes, the unnecessary DC offset circuitry is removed, preventing noise injection and reducing power consumption while maintaining first-order mismatch noise shaping capability
Solution Approach 2:
The patent inverts the conventional approach by modifying the element rotation algorithm to accept signed codes directly, rather than converting signed codes to non-negative codes and then adding a DC offset. This reversal eliminates the need for DC offset circuitry and its associated noise and power waste
2Measurement precision
If two identical DACs are used to form a pseudo-differential DAC, then high-performance conversion is achieved, but power and area efficiency are reduced and offset currents degrade signal-path noise performance
Solution Approach 1:
The patent merges the functionality of two identical DACs into a single DAC by implementing true differential output capability. The modified DWA algorithm dynamically selects elements to produce differential currents directly, eliminating the need for separate DACs and DC offset circuitry, thereby reducing power consumption and area while maintaining high-performance conversion
Solution Approach 2:
The patent makes a single DAC element bank universal by enabling it to produce true differential outputs through modified element selection and rotation. The same DAC elements can generate both positive and negative differential currents dynamically, replacing the need for two dedicated DAC banks and their associated DC offset circuitry
3Ease of manufacture
If signed input codes are converted to non-negative codes for conventional DWA processing, then the algorithm can be implemented, but unnecessary noise is injected and extra power is wasted
Solution Approach 1:
The patent inverts the conventional code conversion approach by modifying the element rotation algorithm to process signed codes directly without conversion to non-negative codes. This reversal eliminates the subsequent DC offset addition step that injects noise, while maintaining full algorithm implementability
Solution Approach 2:
The patent converts the potential harm of signed code processing into a benefit by designing an element rotation algorithm that natively supports signed codes. This transformation eliminates the need for noise-injecting DC offset circuitry, turning what was previously a problematic feature into an advantage for noise reduction
Data Source
AI summary
A system and method dynamically selects digital-to-analog (DAC) circuit elements to provide a True differential-output delta-sigma (ΔΣ) DAC. The sign and magnitude of a received N-bit input code is determined. If the input code comprises a positive value, m+r circuit elements are selected from a plurality of circuit elements by a positive element selector, in which comprises a number of rotational elements, and r circuit elements are selected by a negative element selector. Each selected circuit element comprises a circuit element that was not selected for an immediately preceding received input code and has a corresponding minimum usage count value. If the input digital code comprises a negative value, m+r circuit elements are selected by the negative element selector, and r circuit elements are selected by the positive element selector. The circuit elements are capable of being configured as positive or negative circuit elements.