Differential DAC Encoding for Mismatch-Immune Linearity
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in achieving linearity due to circuit component mismatches, which introduce dynamic non-linearities in the switching output signal, making it difficult to achieve a desired signal-to-noise ratio (SNR) and signal-to-noise-and-distortion ratio (SNDR).
Innovation Solution
The proposed solution involves a DAC design that includes current sources and switches configured to receive differentially-encoded digital signals, with a bias current source or resistor network to produce an analog output signal. This design ensures that errors in the zero value level are self-cancelling, achieving ideal linearity without additional calibration circuitry by using a resistive network or switched current approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DAC designs are used, then device complexity is reduced, but linearity deteriorates due to component mismatches introducing dynamic non-linearities
Solution Approach 1:
The patent employs asymmetric signal encoding where the first and second digital signals are differentially encoded such that overlapping high-value portions and overlapping low-value portions are substantially equal in duration. This asymmetric time-domain distribution causes mismatch errors to produce equal and opposite deviations that cancel each other over time, achieving high linearity without requiring symmetric component matching or complex calibration circuits
Solution Approach 2:
The patent converts the harmful effect of component mismatches into a beneficial self-cancelling mechanism. By designing the differential encoding such that mismatch errors produce symmetric positive and negative deviations, the harmful non-linearities are transformed into canceling error terms that average to zero, thereby achieving high linearity without needing to eliminate the mismatches themselves
2Manufacturing precision
If component mismatches are reduced to improve linearity, then manufacturing precision increases, but device complexity and calibration requirements increase
Solution Approach 1:
The patent implements a self-correcting mechanism where the differential encoding and circuit topology automatically cause mismatch errors to cancel themselves without external intervention. The first and second current sources with their respective switches inherently produce equal and opposite errors that self-neutralize, eliminating the need for external calibration circuits, trimming components, or complex manufacturing processes to achieve high linearity
3Manufacturing precision
If additional calibration circuitry is added to improve linearity, then manufacturing precision increases, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for calibration circuitry by designing the core differential encoding mechanism to inherently self-cancel mismatch errors. By removing the requirement for external calibration components and procedures, the design achieves high linearity with simpler overall device architecture, avoiding the addition of DAC calibration circuits, trimming switches, or test modes
Data Source
AI summary
In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.