Differential DAC Weighting for Monotonic High-Resolution Output
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Solution Overview
Problem
Digital to analog converters (DACs) face challenges in maintaining monotonicity, especially at major carry transitions, as the weights of digital bits are not always exactly desired, leading to non-monotonic analog outputs, which becomes more pronounced with increasing bits and requires stringent component tolerances, making precision control difficult.
Innovation Solution
The solution involves using an N bit differential DAC with true and complementary outputs offset by a half Least Significant Bit (LSB) to create an N+1 bit output, where the transition at major bit transitions involves only the half LSB offset, ensuring monotonicity through appropriate weighting of the N bit DAC's outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC designs are used with increasing number of bits, then resolution increases, but monotonicity cannot be guaranteed due to component tolerance accumulation
Solution Approach 1:
The patent segments the DAC into multiple sub-DACs, each handling a portion of the input bits. By dividing the conversion task across independent sub-DACs with fewer bits each, component tolerance accumulation is reduced while maintaining overall high resolution. The sub-DACs are combined through weighting and summing to achieve the desired resolution without requiring stringent tolerances across all components.
Solution Approach 2:
The patent introduces an intermediary calibration process that measures and characterizes the actual weights of each DAC component. These measured weights are then used to compute calibration coefficients that compensate for tolerance deviations. This intermediary measurement and computation step acts as a mediator between the physical components and the desired monotonic output.
2Reliability
If stringent component tolerances are imposed to maintain monotonicity, then monotonicity is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements self-calibration where the DAC system automatically measures its own component weights and computes correction coefficients without requiring external manual calibration. The system uses its own resources (power, processing capability) to perform the calibration function, eliminating the need for expensive manual adjustment procedures and specialized calibration equipment.
Solution Approach 2:
The patent changes the operational parameters of the DAC by using measured weight values to compute and apply calibration coefficients. Instead of relying on fixed component tolerances, the system dynamically adjusts the effective weights through digital correction factors, allowing standard tolerance components to achieve precision equivalent to much tighter tolerance components.
3Reliability
If calibration is performed to maintain monotonicity in high-bit DACs, then monotonicity is improved, but device complexity increases
Solution Approach 1:
The calibration system uses the DAC's own output and a simple measurement circuit to automatically determine component weights. The same processing resources already present in the DAC are reused to perform the calibration function, eliminating the need for separate complex calibration equipment and reducing overall system complexity.
Solution Approach 2:
The patent uses a simple voltage source and basic measurement circuitry for calibration instead of expensive precision equipment. The calibration process is designed to be computationally simple and quickly executable, making the calibration function inexpensive and low-complexity despite the high precision it achieves.
Data Source
AI summary
Apparatus implementing a monotonic output digital to analog converter (DAC). A high resolution monotonic DAC may be built from a lower resolution DAC using weighting functions that combine the outputs of the lower resolution DAC such that monotonicity is maintained across major carry transitions. The lower resolution DAC should have a true output and a complementary output with a half LSB bias in the output. An extended resolution DAC may be built of; cascaded low resolution DACs; a low resolution DAC in a recursive arrangement with an intermediate storage of its output; or a low resolution DAC with weighting functions that adjust at each of several major carry transition.