Differential-Mode Data Signaling With Common-Mode Clock Extraction
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Solution Overview
Problem
High-speed data communications over backplane electrical links face challenges due to edge-based clock and data recovery limitations, which affect receiver performance.
Innovation Solution
The implementation of data receiver and transmission circuits that simultaneously transmit differential-mode data signals and common-mode clock signals over a pair of transmission lines, using extraction circuits to separate and synchronize these signals, allowing for effective sampling and reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge-based clock and data recovery is used, then data transmission can be achieved, but receiver performance is limited
Solution Approach 1:
The patent segments the transmitted signal into two independent components: a differential-mode data signal and a common-mode clock signal. This segmentation allows the receiver to recover the clock signal separately from the data signal, eliminating the need for complex edge-based clock and data recovery circuits. The common-mode extraction circuit retrieves the clock signal directly from the common-mode component, while the differential-mode circuit retrieves data from the differential-mode component, significantly simplifying the receiver architecture.
Solution Approach 2:
The patent extracts the clock signal from the common-mode component of the transmitted signal using a dedicated common-mode extraction circuit. This extraction approach separates the clock recovery function from the data recovery function, allowing independent optimization of each. The clock signal is taken out directly from the common-mode path without requiring edge detection or complex synchronization circuits, thereby improving receiver performance while reducing complexity.
2Productivity
If differential-mode data signal and common-mode clock signal are transmitted simultaneously, then signal transmission efficiency is improved, but electromagnetic interference may increase
Solution Approach 1:
The patent applies different transmission modes to different signal components based on their specific requirements: differential-mode signaling is used for the data signal to provide noise immunity and reduce electromagnetic interference, while common-mode signaling is used for the clock signal to simplify transmission and enable direct extraction at the receiver. This local quality approach optimizes each signal component's transmission characteristics independently, achieving high transmission efficiency without excessive electromagnetic interference.
Solution Approach 2:
The patent employs asymmetric transmission by sending the data signal in differential-mode (with opposite polarities on the two wires) and the clock signal in common-mode (with identical polarities on the two wires). This asymmetry allows the receiver to easily separate and extract each signal type using corresponding extraction circuits, enabling efficient simultaneous transmission while managing electromagnetic interference through the inherent noise-rejection properties of differential signaling for the data portion.
Data Source
AI summary
A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.