Differential Delay Cells With Back-Gate Timing Control
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Solution Overview
Problem
Existing delay cell circuits in ring oscillators lack fine control over delay time, leading to limited frequency control and increased complexity, especially in differential oscillator applications.
Innovation Solution
A time delay circuit utilizing ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) devices with PMOS and NMOS transistors, where the back-gate terminals of the transistors are connected to modulate the threshold voltage, allowing for linear control of the time delay through a control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional delay cells are used in ring oscillators, then the basic delay function is achieved, but fine control over delay time and frequency is limited
Solution Approach 1:
The patent applies parameter changes by utilizing the back-gate voltage to modulate the threshold voltage of UTBB-FDSOI transistors. By varying the back-gate voltage parameter, the delay time and oscillation frequency can be precisely controlled without changing the basic circuit structure. This resolves the contradiction by enabling fine control (improving ease of operation) through a simple voltage parameter adjustment rather than complex circuit modifications.
Solution Approach 2:
The patent implements dynamics by making the delay cell characteristics adjustable through the back-gate control signal. The delay time becomes a dynamic parameter that can be tuned in real-time by changing the back-gate voltage, transforming a static delay element into a dynamically controllable component. This enables precise control without increasing circuit complexity.
2Measurement precision
If more control mechanisms are added to delay cells for finer delay control, then control precision improves, but circuit complexity increases
Solution Approach 1:
The patent uses parameter changes by exploiting the threshold voltage modulation capability of UTBB-FDSOI transistors through back-gate voltage. This single parameter control (back-gate voltage) provides fine delay control precision without adding complex control circuits, directly resolving the contradiction between precision and complexity.
Solution Approach 2:
The back-gate terminal serves multiple functions: it controls threshold voltage, adjusts delay time, and tunes oscillation frequency all through a single control mechanism. This multi-functionality achieves high control precision without increasing circuit complexity, as one control element performs multiple adjustment tasks.
3Ease of operation
If conventional transistors are used without back-gate control, then device simplicity is maintained, but linear control over threshold voltage is not achieved
Solution Approach 1:
The patent exploits parameter changes in UTBB-FDSOI transistors where the threshold voltage has a linear relationship with the back-gate voltage. This inherent linear characteristic of the transistor parameter provides ease of operation for control applications without requiring complex control circuitry, resolving the contradiction between linear control capability and device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides simple and linear control over the time delay and frequency of delay cells, reducing circuit complexity, noise, and power consumption, while enabling rail-to-rail input range and near-instantaneous response to control signals.
Implementation Method 1
each of said transistors has a back-gate terminal and is arranged such that a respective threshold voltage of said transistor is linearly dependent on a respective voltage applied to the back-gate terminal of said transistor
Data Source
AI summary
A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.