Differential Signal Deskew Circuit With Buffered Impedance Isolation
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Solution Overview
Problem
Existing deskew circuits for differential signals face challenges in meeting impedance matching requirements, especially at high-speed transmission rates, due to variations in transmission cable lengths causing delay skew, and existing solutions often compromise terminal impedance.
Innovation Solution
A deskew circuit design incorporating a voltage buffer circuit with high input impedance, isolating the second common mode voltage generating circuit from the signal input terminal, allowing flexible impedance configuration while maintaining impedance matching, comprising a first common mode voltage generating circuit, a voltage buffer circuit, a second common mode voltage generating circuit, and an output circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay device is disposed to compensate for delay skew, then the delay skew of the differential signal pair is improved, but the impedance matching requirement cannot be met
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between the differential signal input and the delay compensation circuit. This buffer circuit has high input impedance that isolates the impedance matching requirement from the delay compensation circuit, allowing the delay device to compensate for skew without affecting the terminal impedance matching.
Solution Approach 2:
The circuit is divided into separate functional modules: an input buffer stage for impedance matching, a delay compensation stage for skew correction, and an output stage. This segmentation allows each module to be optimized independently - the buffer handles impedance matching while the delay circuit handles skew compensation without interfering with each other.
2Productivity
If transmission rate is increased, then productivity is improved, but delay skew becomes more significant and harder to compensate
Solution Approach 1:
The buffer circuit performs preliminary signal conditioning and impedance matching before the signal enters the delay compensation stage. This preliminary action prepares the signal for high-speed transmission by establishing proper impedance conditions, enabling more effective delay skew compensation at higher transmission rates.
Data Source
AI summary
A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.