Differential DFE Receiver Layout for Smaller HBM Interface Circuits

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Solution Overview

Problem

Existing receiving circuits for High-Bandwidth Memory (HBM) face challenges in minimizing area and power consumption due to the use of Decision Feedback Equalizers (DFE) with multiple input stages, which increase the size of the chip and complicate signal processing.

Innovation Solution

A simplified Decision Feedback Equalizer (DFE) with two or more differential signal path units, each including a summer and a latch, operates at different clocks and adjusts offsets using transistor arrays for input and output stages, reducing the circuit area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing receiving circuits use equalizers with multiple input stages including offset and DFE functionalities, then signal processing capability is improved, but the area of the receiving circuit chip increases

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidreceiving circuit chip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines offset control and DFE functionalities into a single input stage by using a shared summer unit that processes both offset signals and DFE feedback signals simultaneously. This merging eliminates the need for separate input stages, thereby reducing the receiving circuit chip area while maintaining signal processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The summer unit is designed to perform multiple functions: it processes the data signal, adds offset control signals, and incorporates DFE feedback signals all within the same circuit block. This multi-functional design allows a single unit to replace what would traditionally require multiple dedicated units, thus reducing overall circuit area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If DFE circuits with multiple input stages are used to control offset and DFE functionalities, then signal correction capability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal correction capabilityVSAvoidDFE circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple control functions into a unified DFE circuit structure where a single summer unit handles both offset correction and DFE signal addition. This consolidation reduces the number of separate control paths and circuit blocks, thereby simplifying the overall device complexity while preserving signal correction capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies different signal processing operations at different stages within the same circuit block. The summer unit selectively adds offset signals during certain phases and DFE feedback signals during other phases, allowing complex functionality to be achieved through localized, phase-dependent operations rather than through globally complex circuitry.

Inventive Principle:
Principle #3Local quality

3Reliability

If multiple input stages are used in equalizers, then equalization performance is improved, but power consumption increases

Engineering Contradiction:
Improveequalization performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple equalization functions into a single active input stage that processes all signals (data, offset, and DFE feedback) through one summer unit. This eliminates the need for multiple independently powered input stages, thereby reducing total power consumption while maintaining equalization performance through coordinated signal processing within the unified structure.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12470439B2Apparatus for receiving data from memory
Publication Date: 2025.11.11 ELECTRONICS & TELECOMM RES INST
  • US12470439B2 patent drawing
  • US12470439B2 patent drawing
  • US12470439B2 patent drawing

AI summary

Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.