Differential Interpolative Divider for Low-Jitter Clock Division
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Solution Overview
Problem
Interpolative dividers are sensitive to power supply noise and stray signal coupling, requiring large amounts of decoupling capacitance that do not scale with technology feature size reduction, making them area-expensive and limiting their efficiency.
Innovation Solution
A differential phase interpolator structure with high active power supply rejection and coupling rejection is employed, reducing the need for decoupling capacitance and improving jitter and spur performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interpolative divider structure is used, then decoupling capacitance is required to reject power supply noise and stray signal coupling, but this increases decoupling area requirements and reduces manufacturing efficiency
Solution Approach 1:
The patent replaces passive decoupling capacitance with an active differential phase interpolator structure that uses controlled current sources and capacitive switching to achieve power supply rejection and stray signal coupling rejection, eliminating the need for large decoupling capacitors
Solution Approach 2:
The patent employs a differential structure combining multiple current sources and capacitors working together to provide high active power supply rejection and coupling rejection, achieving superior performance without requiring additional decoupling area
2Reliability
If large decoupling capacitance is used to reject power supply noise and stray signal coupling, then power supply rejection improves, but device area increases and does not scale with technology feature size reduction
Solution Approach 1:
The patent substitutes passive decoupling capacitance with an active differential phase interpolator that uses controlled current sources and switching mechanisms to achieve stray signal coupling rejection, enabling area reduction and improved scalability with technology feature size
Solution Approach 2:
The patent changes the approach from using large fixed capacitance values to using controlled current sources and switching elements whose parameters can be dynamically adjusted, achieving the same rejection performance with reduced area and improved scalability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The differential structure significantly decreases decoupling area requirements, allowing more interpolative dividers on a die or improving performance with the same area, achieving lower jitter and spurs.
Implementation Method 1
A first capacitor in the phase interpolator is charged using a first current source during a first part of a charging cycle
Implementation Method 2
A second capacitor in the phase interpolator is charged using a second current source during a second part of a charging cycle
Implementation Method 3
A comparator in the phase interpolator compares a first voltage across the first capacitor and a second voltage across the second capacitor
Data Source
AI summary
An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0≤k≤M, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the the first voltage equals the second voltage.