Differential Interpolative Divider for Power Noise Rejection

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Solution Overview

Problem

Interpolative dividers are sensitive to power supply noise and stray signal coupling, requiring large amounts of decoupling capacitance that do not scale with technology feature size reduction, making them area-expensive and limiting their effectiveness.

Innovation Solution

A differential phase interpolator design with symmetric architecture reduces the need for decoupling capacitance by employing a differential topology with active power supply and coupling rejection, using two current sources and capacitors to minimize noise impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional interpolative divider design is used, then decoupling capacitance provides noise rejection, but decoupling area becomes large and does not scale with technology feature size reduction

Engineering Contradiction:

Improvenoise rejectionVSAvoiddecoupling area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent replaces passive decoupling capacitance with an active differential phase interpolator architecture that uses current sources and capacitors in a differential configuration to actively reject power supply noise and stray signal coupling, eliminating the need for large decoupling capacitance

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the architectural parameters from single-ended to differential topology, using symmetric current sources and capacitors that provide active rejection of noise while maintaining functionality with significantly reduced area

Inventive Principle:

Principle #35Parameter changes

2Object-affected harmful factors

If large decoupling capacitance is used, then power supply noise and stray signal coupling are rejected, but device area increases making it area-expensive

Engineering Contradiction:

Improvepower supply noise rejectionVSAvoidtotal device area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent substitutes the mechanical approach of using large passive decoupling capacitance with an active differential circuit architecture that inherently rejects noise through its symmetric topology and active current sources

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent converts the harmful effect of power supply noise and signal coupling into a benefit by using the differential architecture to actively measure and reject these disturbances, turning potential interference into a mechanism for improved noise rejection

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12425041B2Interpolative divider

Publication Date: 2025.09.23 SKYWORKS SOLUTIONS INC

AI summary

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0≤k≤M, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.