Differential Digital-to-Time Converters for Low-Noise DPLLs
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Solution Overview
Problem
Existing digital phase-locked loops face challenges with non-linearity and noise in digital-to-time converters (DTCs), particularly due to capacitor mismatch and supply-induced delays, which affect the accuracy and efficiency of high-frequency clock signal generation.
Innovation Solution
Implementing a differential digital-to-time converter (DTC) structure where the sum of delays in two delay lines is kept constant, reducing integral non-linearity (INL) and supply sensitivity, and using the same supply for both lines to minimize area overhead and noise, with a sigma-delta module for control signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-ended DTC is used to delay the reference clock signal, then the delay range can cover one high frequency clock period, but integral non-linearity (INL) increases and supply-induced delay variation affects accuracy
Solution Approach 1:
The single-ended DTC is segmented into two separate delay lines (first and second delay lines) that operate differentially. Each delay line processes one phase of the differential reference clock signal, dividing the overall delay function into two complementary parts that can be controlled independently to achieve better linearity and supply rejection.
Solution Approach 2:
The differential delay lines are designed with asymmetric delay control where the sum of delays in the two delay lines is kept constant while their difference varies. This asymmetric control strategy allows the delay difference to be both positive and negative, expanding the effective delay range while maintaining constant total delay to reject supply variations.
2Measurement precision
If the delay range of a DTC is increased to cover one high frequency clock period, then the quantization noise is minimized, but the chain length must be very long which increases area
Solution Approach 1:
The differential DTC employs dynamic delay control where the delay amounts in the two delay lines are adjusted in opposition to each other. When one delay line increases its delay, the other decreases by a corresponding amount, maintaining constant sum. This dynamic adjustment allows achieving the required delay range with shorter physical chains compared to a single-ended design.
3Reliability
If a differential DTC is implemented with two delay lines, then supply sensitivity is reduced and linearity is improved, but the device complexity increases
Solution Approach 1:
The differential DTC merges the functions of delay generation and supply rejection into a single integrated structure. By combining two delay lines that share the same supply voltage and using differential signaling throughout, the design achieves supply insensitivity without requiring separate reference paths or additional compensation circuits, thus limiting the increase in device complexity.
4Extent of automation
If capacitor-based DTC implementation is used, then the delay can be controlled digitally, but linearity and noise performance are degraded
Solution Approach 1:
The patent changes the fundamental operating parameters of the DTC by transitioning from single-ended to differential operation and from fixed delay to dynamically adjustable delay with constant sum constraint. These parameter changes enable digital control to be achieved while simultaneously improving linearity, as the differential architecture compensates for capacitor mismatch and non-linearities through its inherent symmetry and balance.
Data Source
Figure 1~2
Figure 3
Figure 4a~4b
AI summary
A method and architecture for providing improved linearity and reduced noise in a digital phase-locked loop is described in which a differential time-to-digital converter (710) is implemented. Digital-to-time converters (780, 830) are used for adjusting a reference clock signal (750) based on fractional change signal (820a), and, for adjusting a feedback signal (760) based on fractional change signal (820b). Each fractional change signals (820a, 820b), centred about a midpoint, M, comprises (M+x) and (M-x) respectively, x being the fraction. By implementing a differential time-to-digital converter (710), the sum of delays in each input path is kept constant so that integral non-linearity is significantly improved. Supply sensitivity is also greatly reduced as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the required delay range of a differential digital-to-time converter (780; 830) is half that of a single input digital-to-time converter.