Differential Duty Cycle Correction With Lock-Based Feedback
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Solution Overview
Problem
Conventional duty cycle correction circuits in System-on-Chips (SoCs) face accuracy issues at high frequencies and consume significant power due to the difficulty in detecting small differences in duty cycles, leading to errors and reliability degradation.
Innovation Solution
A duty cycle correction circuit comprising a duty cycle adjuster, a lock signal generator, and a correction bit generator, which iteratively adjusts differential input signals based on correction bits and generates a lock signal to accurately correct duty cycle distortion, reducing power consumption by deactivating components when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional duty cycle correction circuit uses a comparator to detect small duty cycle differences, then the circuit can correct duty cycle distortion, but the accuracy of the comparator is affected and the correction accuracy decreases at high frequencies
Solution Approach 1:
The patent uses a dynamic correction approach where the correction amount is adjusted based on the detected duty cycle difference. The circuit iteratively refines the correction by dynamically changing the correction amount, allowing accurate detection and correction even at high frequencies where static comparator methods fail.
Solution Approach 2:
The patent implements a feedback mechanism where the duty cycle detector continuously monitors the corrected signal and feeds back to the duty cycle adjuster. This closed-loop feedback system enables the circuit to maintain high accuracy by continuously adjusting the correction based on actual performance, resolving the accuracy issue at high frequencies.
2Reliability
If the duty cycle correction circuit operates continuously to maintain correction accuracy, then the correction performance is maintained, but the power consumption increases significantly
Solution Approach 1:
The patent employs periodic action by enabling the duty cycle correction circuit only when needed. The controller activates the correction circuit based on detection of duty cycle distortion, and deactivates it when the signal is already within the acceptable range. This periodic operation maintains correction performance while significantly reducing power consumption during normal operation.
Solution Approach 2:
The circuit uses a controller that automatically detects when correction is needed and activates the correction circuit accordingly. This self-service mechanism eliminates the need for continuous operation, as the system autonomously determines when power should be consumed to maintain correction accuracy.
3Use of energy by moving object
If the duty cycle correction circuit is activated only when distortion is detected, then power consumption is reduced, but the response time to correct distortion increases
Solution Approach 1:
The patent implements preliminary action by having the duty cycle detector continuously monitor the signal characteristics in advance. When distortion beyond the threshold is detected, the correction circuit is immediately activated. This preliminary detection and preparedness ensures rapid response time while avoiding continuous operation of the full correction circuit, thus balancing power consumption with response time.
Data Source
AI summary
A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.