Differential Equalizer Resonant Feedback for High-Frequency ISI
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Solution Overview
Problem
Traditional differential equalizers are inadequate for compensating intersymbol interference (ISI) at higher frequency communications, leading to significant eye jitter and unreliable clock and data recovery in wireline receivers, due to limitations in gain-versus-frequency slope characteristics and increased power consumption.
Innovation Solution
The implementation of equalizers with resonant circuits in source degeneration and feedback circuits, which tailor the gain-frequency response to effectively compensate for ISI across a broader bandwidth, including the use of voltage-to-current and current-to-voltage converters with adjustable resistors and capacitors to optimize gain and frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional equalizers are used for lower-frequency transmissions, then ISI compensation is adequate at those frequencies, but they cannot adequately compensate for higher ISI inherent in increasingly higher frequency communications
Solution Approach 1:
The equalizer employs adjustable gain stages with variable gain control, allowing the gain-versus-frequency characteristics to be dynamically adapted to different transmission frequencies. This enables the equalizer to maintain optimal ISI compensation performance across a wide frequency range from lower to higher frequencies by adjusting the gain parameters according to the specific operating conditions
Solution Approach 2:
The equalizer changes its operational parameters (gain values, bandwidth settings) to match different frequency requirements. By modifying these parameters, the equalizer can effectively compensate for ISI at both lower and higher frequencies, resolving the contradiction between being optimized for specific frequencies and being adaptable across frequency ranges
2Reliability
If multiple branches of cascaded differentiator circuits are included to tackle ISI issues, then ISI compensation capability is improved, but capacitive parasitic limits the high-speed capacity
Solution Approach 1:
The patent extracts and eliminates the problematic capacitive parasitic elements from the circuit design by using an alternative architecture that does not rely on multiple cascaded differentiator circuits. This removal of harmful capacitive effects allows the equalizer to maintain high-speed capacity while still providing effective ISI compensation through a different circuit topology
3Reliability
If many gain stages are used in equalizer designs, then ISI compensation performance is improved, but power consumption is significantly increased
Solution Approach 1:
The equalizer uses a minimized number of gain stages, applying only the necessary amount of gain compensation required for effective ISI correction. By avoiding excessive gain stages, the design achieves adequate ISI compensation performance while keeping power consumption low, rather than using more stages than necessary
4Reliability
If equalizers are designed with higher gain-versus-frequency slope characteristics at higher frequencies, then compensation for frequency-dependent losses is improved, but device complexity increases
Solution Approach 1:
The equalizer applies different gain characteristics to different frequency regions, with higher gain-versus-frequency slope characteristics specifically at higher frequencies where frequency-dependent losses are more severe. This localized optimization provides effective compensation for frequency-dependent losses without requiring complex circuitry across the entire frequency spectrum
Data Source
AI summary
An embodiment of an equalizer includes a voltage-to-current converter and a current-to-voltage converter. The voltage-to-current converter is configured to convert a differential input voltage to a differential current, and includes a differential amplifier with a first transistor and a second transistor, and a first source degeneration circuit coupled between the first transistor and the second transistor. An embodiment of the first source degeneration circuit includes a first resonant circuit. The current-to-voltage converter is coupled to the voltage-to-current converter, and is configured to convert the differential current to a differential output voltage. The current-to-voltage converter includes a first inverter with a first feedback circuit and a second inverter coupled to the first inverter, which includes a second feedback circuit. An embodiment of the first feedback circuit includes a second resonant circuit, and an embodiment of the second feedback circuit includes a third resonant circuit.