Differential Etch Stop Layer for FinFET Source/Drain Protection
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Solution Overview
Problem
In the semiconductor industry, particularly for FinFET devices, the challenge lies in forming differential layers such as the Contact Etch Stop Layer (CESL) that can effectively differentiate deposition rates on horizontal and vertical surfaces, which is crucial for protecting source/drain regions and increasing the process window for component formation, as existing methods struggle to achieve this differentiation efficiently.
Innovation Solution
Implementing a directional plasma activation process during the deposition of the CESL, using techniques like Plasma Enhanced Atomic Layer Deposition (PEALD) or Chemical Vapor Deposition (CVD) with in situ plasma activation, to enhance the deposition rate on surfaces with a horizontal component, resulting in thicker horizontal portions compared to vertical portions, thereby creating a differential thickness profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deposition methods are used for CESL, then deposition is uniform across all surfaces, but this fails to provide differential protection for source/drain regions versus gate spacers
Solution Approach 1:
The patent applies local quality by creating a CESL with spatially varying thickness: thicker portions over source/drain regions provide enhanced protection, while thinner portions over gate spacers allow better etch access. This non-uniform thickness distribution is achieved through controlled deposition processes that respond to local surface properties or masking strategies, enabling differential protection where it is most needed without compromising other structures.
Solution Approach 2:
The CESL is segmented into functionally distinct regions with different thicknesses. The layer is divided into thicker segments over active source/drain areas and thinner segments over inactive gate spacer areas. This segmentation allows each region to fulfill its specific function optimally: thick regions provide robust protection against etch damage, while thin regions permit necessary etch penetration for subsequent processing steps.
2Ease of manufacture
If uniform thickness CESL is formed, then manufacturing is simpler, but process window for forming other components is reduced
Solution Approach 1:
The patent employs parameter changes by varying the deposition parameters (such as deposition rate, temperature, or precursor flow rates) during CESL formation to create different thicknesses in different regions. This dynamic adjustment of deposition parameters during the process enables the formation of a differential CESL profile, expanding the process window for subsequent component formation while maintaining manufacturing feasibility through controlled parameter modulation.
3Reliability
If thicker CESL is deposited on vertical surfaces, then gate spacer protection is improved, but source/drain region protection is insufficient
Solution Approach 1:
The patent inverts the conventional approach by making the CESL thicker where it is needed most for protection (over source/drain regions) rather than uniformly thick or thicker on vertical surfaces. This inverted thickness distribution strategy ensures that etch stop capability is maximized at the source/drain regions where etch damage risk is highest, while gate spacers receive adequate but not excessive protection, optimizing the balance between protection and etch access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for greater protection of source/drain regions and increases the process window for forming other components, improving the reliability and performance of semiconductor devices by enabling more precise control over layer thickness and etch stop capabilities.
Implementation Method 1
Implementing a directional plasma activation process during the deposition of the CESL, using techniques like Plasma Enhanced Atomic Layer Deposition (PEALD) or Chemical Vapor Deposition (CVD) with in situ plasma activation
Data Source
AI summary
Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.