Differential Feedback LNA Circuit for Lower Noise and Wider Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional common drain feedback low noise amplifiers face challenges in reducing input capacitance and noise due to parasitic capacitance and limited adjustment range of NMOS transistors, which narrows the bandwidth and increases noise.
Innovation Solution
A semiconductor integrated circuit device with a feedback circuit that includes a first transistor generating a bias current, where a signal with a reverse phase to the output signal is input to the gate of the transistor, allowing for additional feedback paths and reduced parasitic capacitance, thereby decreasing the mutual conductance and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common drain circuit is connected between input and output of the amplifier, then feedback is provided to improve noise performance, but parasitic capacitance of the common drain circuit narrows the bandwidth of input matching
Solution Approach 1:
The common drain circuit is divided into two separate common drain circuits, each providing feedback to a different input terminal of the differential amplifier. This segmentation allows independent optimization of each feedback path, reducing the overall parasitic capacitance impact on bandwidth while maintaining noise performance benefits.
Solution Approach 2:
The patent transitions from a single-ended feedback architecture to a differential feedback architecture by adding another dimension to the feedback path. This allows the feedback signal to be distributed differentially, effectively doubling the available bandwidth for input matching while maintaining the noise cancellation benefits of the common drain configuration.
2Speed
If the size of NMOS transistors is reduced to minimize parasitic capacitance, then bandwidth improves, but the adjustment range of the transistors becomes limited
Solution Approach 1:
The patent changes the operating parameters of the NMOS transistors by applying reverse-phase signals to their gates. This allows the transistors to operate in an optimized region that simultaneously achieves low parasitic capacitance for high bandwidth and maintains sufficient adjustment range for proper feedback control, resolving the trade-off between size reduction and adaptability.
3Speed
If additional feedback paths are added to reduce parasitic capacitance, then bandwidth increases, but device complexity increases
Solution Approach 1:
The patent makes the common drain circuits multi-functional by having them simultaneously provide noise cancellation feedback and bandwidth extension through the reverse-phase signal mechanism. This universality allows the same feedback paths to achieve multiple objectives without requiring separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
Data Source
AI summary
According to an embodiment, a semiconductor integrated circuit device includes an amplifier and a feedback circuit. The amplifier includes an input terminal receiving an input signal and an output terminal outputting an output signal. The feedback circuit includes a first transistor generating a bias current. The feedback circuit is configured to operate based on the bias current. The feedback circuit is configured to receive the output signal to supply a feedback signal to the input terminal. A signal having a reverse phase to the output signal is input to a gate of the first transistor.