Differential Flash Memory Cell Endurance via Segmentation
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Solution Overview
Problem
Conventional flash memory cell designs face limitations in endurance due to degradation of tunnel oxide during Program/Erase cycles, leading to reduced ability to distinguish between programmed and erased states, which affects the reliability and performance of semiconductor devices.
Innovation Solution
A differential flash memory cell design is introduced, where two memory cells with complementary threshold voltages are used, allowing for the detection of a differential current to determine logic states without relying on external reference levels, thereby reducing the read window and increasing endurance through optimized programming and read mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory cell designs are used, then the structure is simple and manufacturing is easier, but the tunnel oxide degrades during Program/Erase cycles reducing endurance
Solution Approach 1:
The flash memory cell is divided into two separate cells (first memory cell and second memory cell) with complementary threshold voltages. Each cell is read independently and their currents are compared differentially. This segmentation allows the read operation to be reference-free, eliminating the need for external reference levels and reducing the read window, thereby improving endurance without requiring complex additional structures.
Solution Approach 2:
The patent transitions from a single-cell architecture to a differential two-cell architecture, adding a dimensional aspect to the memory cell design. By comparing the output currents of two cells with opposite threshold voltage polarities, the system creates a differential read mechanism that operates in a new dimensional space, improving reliability by eliminating tunnel oxide degradation effects from the read window.
2Reliability
If external reference levels are used for reading, then the read mechanism is simpler, but the read window is larger reducing endurance
Solution Approach 1:
The patent extracts and eliminates the external reference level from the read mechanism. By using two memory cells with complementary threshold voltages whose currents are compared differentially, the system removes the need for external reference voltages. This extraction of the reference element reduces the read window and improves endurance, though it requires a slightly more complex differential read mechanism.
3Reliability
If the read window is reduced to improve endurance, then tunnel oxide degradation is minimized, but the ability to distinguish logic states becomes more difficult
Solution Approach 1:
The patent employs asymmetry by designing the two memory cells with complementary threshold voltages of opposite polarity. This asymmetric design creates a differential current relationship where one cell conducts while the other blocks, or vice versa, depending on the stored logic state. This asymmetric complementary structure enhances the differential signal amplitude, making logic state detection easier even with a reduced read window, thereby improving endurance without sacrificing detectability.
Solution Approach 2:
The patent creates a copy of the memory cell structure with inverted threshold voltage characteristics. The second memory cell is essentially a complementary copy of the first, with opposite polarity threshold voltage. By comparing the outputs of these complementary copies, the system achieves differential reading that amplifies the signal for easy detection while maintaining a small read window for improved endurance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The differential cell design enhances the number of allowable Program/Erase cycles, improves device reliability, and allows for optimized read speed and power consumption by adjusting the read voltage and current, thereby extending the functional lifespan of flash memory devices.
Implementation Method 1
EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling
Implementation Method 2
The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate
Data Source
AI summary
A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method includes reading the first and second memory cells to determine a current associated with the first and second threshold voltages. The first threshold voltage is equal to a first value and the second threshold voltage is equal to a second value. The method further includes determining if the first current corresponds to a predetermined logic state. If the current does not correspond to the predetermined logic state, the first and second memory cells are programmed. The programming includes changing the first threshold voltage from the first value to a third value and the second threshold voltage from the second value to a fourth value.