Differential D-Type Flip-Flop for Phase-Aligned Complementary Outputs
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Solution Overview
Problem
Conventional flip-flops generate inverted and non-inverted signals with a phase difference due to separate paths and additional inverters, leading to delays and alignment issues in integrated circuits, particularly affecting combinational elements like decoders and multiplexers.
Innovation Solution
The design employs differential flip-flops with identical data paths for both inverted and non-inverted signals, using cross-coupled circuits and feedback loops to ensure simultaneous generation without phase difference, suitable for 5 nm and 7 nm FINFET technology, and optionally includes set/reset functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate paths and additional inverters are used to generate inverted and non-inverted signals, then signal generation is achieved, but phase difference and delays occur
Solution Approach 1:
The patent merges the generation of inverted and non-inverted signals into a single unified flip-flop circuit path. The differential flip-flop structure processes both signals through the same sequential logic path, eliminating the need for separate paths and additional inverters that caused phase differences and delays in conventional designs.
Solution Approach 2:
Instead of generating the inverted signal by passing it through additional inverters after the flip-flop (conventional approach), the patent inverts the approach by using differential signaling throughout the entire flip-flop circuit. The inverted and non-inverted signals are generated simultaneously from the same input through complementary transistor pairs, ensuring they remain in phase.
2Reliability
If differential flip-flops with identical data paths are used, then phase difference is eliminated, but device complexity increases
Solution Approach 1:
The patent applies homogeneity by creating identical data paths for both inverted and non-inverted signals within the differential flip-flop. Both signals traverse the same number of logic stages with matching transistor sizes and configurations, ensuring equal propagation delays and simultaneous arrival at their respective outputs, thereby eliminating phase differences.
3Device complexity
If conventional flip-flops are used, then device complexity is reduced, but worst-case delays and glitches occur in combinational elements
Solution Approach 1:
The patent creates equipotential conditions for signal propagation by designing matched transistor pairs with identical characteristics in the critical signal paths. The differential structure ensures that both inverted and non-inverted signals experience equal electrical conditions and propagation delays, eliminating the worst-case delay variations that plague conventional asymmetric flip-flop designs.
Data Source
AI summary
A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.