Differential Frequency Doubler With Cascode Harmonic Rejection
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Solution Overview
Problem
High-frequency RF systems face challenges in generating signals at mm-wave frequencies due to poor phase noise performance and low output power, particularly in oscillators and frequency dividers, and existing frequency multipliers struggle to provide high output power and reject fundamental input frequencies effectively.
Innovation Solution
A frequency doubling circuit is implemented using a differential transistor pair coupled with a cascode stage and transmission line elements, along with a harmonic filter to enhance gain and output power, and reject fundamental frequencies, achieving high conversion gain and output power at the second harmonic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If oscillators operate at high frequencies to generate mm-wave signals, then the operating frequency is improved, but phase noise performance deteriorates and output power decreases
Solution Approach 1:
The frequency generation process is segmented into two stages: a VCO operating at a lower frequency (f/2) followed by a frequency doubler stage. This segmentation allows the VCO to operate at a frequency where it can maintain good phase noise performance while the frequency doubling function handles the mm-wave generation, thus resolving the contradiction between high operating frequency and phase noise performance.
2Speed
If oscillators operate at high frequencies to generate mm-wave signals, then the operating frequency is improved, but output power deteriorates
Solution Approach 1:
The frequency generation system is divided into a power-efficient VCO stage operating at lower frequency and a frequency doubling stage that provides the necessary output power at mm-wave frequencies. This segmentation resolves the contradiction by allowing each stage to operate in its optimal performance region.
3Speed
If frequency multipliers are used to generate high frequency signals, then the output frequency is improved, but the ability to reject fundamental input frequency deteriorates
Solution Approach 1:
A differential cascode pair is introduced as an intermediary stage between the VCO and the output. This cascode stage provides impedance transformation and frequency multiplication while inherently suppressing the fundamental frequency through its differential operation and impedance characteristics, thus resolving the contradiction between high frequency output and fundamental frequency rejection.
4Speed
If frequency dividers are used in PLLs at high frequencies, then the operating frequency is improved, but power consumption deteriorates
Solution Approach 1:
Instead of using frequency division to achieve high frequency operation, the invention inverts the approach by using frequency multiplication from a lower frequency VCO. This inversion eliminates the need for high-frequency frequency dividers in the PLL, thereby reducing power consumption while maintaining high frequency operation.
Data Source
AI summary
In accordance with an embodiment, a frequency doubling circuit includes a differential transistor pair coupled to an input port of the frequency doubling circuit, a first differential cascode stage having an input coupled to an output of the differential transistor pair, a plurality of first impedance elements coupled between the output of the differential transistor pair and the input of the first differential cascode stage, and an output combining network coupled between the first differential cascode stage and an output port of the frequency doubling circuit.