Differential Signal Line Layout for Lower-Parasitic IC Wiring
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Solution Overview
Problem
The traditional semiconductor integrated circuit design with gates of transistors arranged in a line results in complex wiring shapes for clock signal lines, leading to increased parasitic capacitance and manufacturing variations.
Innovation Solution
A semiconductor integrated circuit design where positive and negative signal lines are wired along a predetermined direction, connecting gates of positive and negative transistors to their respective output terminals, simplifying the wiring shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If gates of transistors are arranged in a line and clock signal lines are wired linearly, then the wiring shape becomes simple, but the signal lines need to be bent or divided to reach latches arranged in a different direction, complicating the wiring shape
Solution Approach 1:
The patent changes the arrangement direction of latches to match the direction of signal line wiring. By arranging latches in the same direction as the gate arrangement (horizontal direction), the signal lines can extend linearly from output circuits to latches without bending or division, resolving the wiring complexity issue while maintaining simple linear wiring shapes
2Adaptability or versatility
If signal lines are bent or divided to reach latches, then the signal can be distributed to all components, but parasitic capacitance increases
Solution Approach 1:
By rearranging latches in the horizontal direction (same as gate arrangement), the patent enables direct linear signal line connections without bends or divisions. This maintains effective signal distribution to all latches while eliminating the parasitic capacitance increases that would result from bent or divided signal lines
3Adaptability or versatility
If signal lines have complex wiring shapes, then flexibility in component arrangement is improved, but manufacturing variation increases
Solution Approach 1:
The patent achieves component arrangement flexibility by changing the latch arrangement direction to match the signal line wiring direction. This creates a standardized linear wiring pattern that reduces manufacturing variation while still allowing flexible arrangement of circuit blocks through the consistent directional layout
Data Source
AI summary
In a semiconductor integrated circuit in which a pair of signal lines is wired, the wiring shape of these signal lines is simplified.An output circuit outputs a predetermined differential signal from a positive output terminal and a negative output terminal. A plurality of positive transistors and a plurality of negative transistors are disposed in a logic circuit. Gates of the plurality of positive transistors are arranged in a predetermined direction. Gates of the plurality of negative transistors are arranged in a predetermined direction. A positive signal line is wired from the positive output terminal along the predetermined direction, and connects each of the gates of the plurality of positive transistors and the positive output terminal. A negative signal line is wired from the negative output terminal along the predetermined direction, and connects each of the gates of the plurality of negative transistors and the negative output terminal.