Differential Input Buffer Latching for Fast Low-Power DRAM I/O
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high data reliability, fast memory access, and reduced power consumption while accommodating a wide range of input signals, particularly in low-power double data rate synchronous DRAM applications, where existing input receiver circuits struggle to efficiently process address, command, and clock signals.
Innovation Solution
The implementation of a data latch type input buffer with differential amplifiers that amplify data signals and latch them based on a voltage difference between the data input signal and a reference voltage, utilizing a voltage control circuit and an internal data strobe generator to manage signal precharging and amplification during each clock cycle, ensuring efficient data transfer and reduced power noise propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If input receiver circuits use faster operation to increase access speed, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The input receiver circuit dynamically adjusts its operating characteristics based on signal conditions. The differential amplifier operates in different modes (linear vs. saturated) depending on the input signal voltage level, allowing fast response when needed while consuming less power during normal operation. This dynamic adaptation resolves the contradiction between speed and power consumption.
Solution Approach 2:
The circuit changes its operating parameters (gain, bandwidth, power consumption) based on the input signal characteristics. When the input signal is within the optimal range, the circuit operates with standard parameters; when signals are weak or strong, it adjusts parameters to maintain performance while managing power consumption, thus resolving the speed-power tradeoff.
2Adaptability or versatility
If input receiver circuits accommodate a wide range of input signals, then adaptability is improved, but measurement precision deteriorates
Solution Approach 1:
The differential amplifier dynamically adjusts its gain and operating point based on the input signal amplitude. For weak signals, it operates with higher gain to maintain detection precision; for strong signals, it reduces gain to avoid saturation. This dynamic adjustment allows the circuit to accommodate a wide signal range while maintaining precision across different signal levels.
Solution Approach 2:
The circuit changes its transfer characteristics and operating parameters according to the input signal strength. By adjusting the amplifier's gain and bias conditions, it optimizes the transfer function for different signal ranges, thereby maintaining measurement precision while accommodating diverse input signal amplitudes as required by LPDDR4 specifications.
3Reliability
If differential amplifiers amplify voltage difference between data input and reference voltage, then data reliability is improved, but power noise propagation increases
Solution Approach 1:
The circuit extracts and separates the signal amplification function from the power distribution function. By using dedicated power supply voltages (VDDQ, VDDQ2) and isolating the differential amplifier's power consumption from the main data bus, it prevents power noise from propagating through the data path while maintaining reliable signal amplification.
Solution Approach 2:
The reference voltage (VREF) acts as an intermediary that enables differential amplification without directly coupling power noise to the data path. The differential amplifier compares the data signal against VREF, and by using separate power supply rails for the amplifier, it isolates power noise from the amplified data output, thus maintaining data reliability while managing power noise propagation.
Data Source
AI summary
Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.