Differential Input Circuit Calibration for Memory Duty Cycle Drift
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Solution Overview
Problem
The increasing demand for faster semiconductor memory with precise duty cycle control poses challenges in maintaining accurate internal clock signals, as differential input circuits can cause duty cycle deviations, affecting reading and writing performance if not properly calibrated and monitored.
Innovation Solution
A calibration circuit that includes a differential input circuit, a comparison unit, and a logical unit to stabilize the duty cycle of internal signals by comparing and adjusting them to ensure they remain within a preset range, thereby reducing deviations and improving memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If differential input circuit is used to generate internal clock signals, then memory operation speed can be increased, but duty cycle deviation occurs affecting reading and writing performance
Solution Approach 1:
The patent applies preliminary action by performing duty cycle calibration before memory operations. The calibration circuit pre-adjusts the internal clock signals generated by the differential input circuit to correct duty cycle deviations, ensuring accurate timing for subsequent high-speed read and write operations.
Solution Approach 2:
The patent implements feedback through a duty cycle monitoring mechanism that detects deviations in the internal clock signals and feeds this information back to the calibration circuit. This feedback loop enables continuous correction of duty cycle errors, maintaining precision despite the high-speed operation enabled by the differential input circuit.
2Manufacturing precision
If duty cycle calibration circuit is added to correct deviations, then duty cycle accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration circuit and monitoring circuit functions into the existing memory structure. By integrating these functions with the differential input circuit and memory controller, the patent reduces overall device complexity while maintaining duty cycle accuracy through shared components and coordinated operation.
Solution Approach 2:
The patent applies universality by designing the calibration and monitoring circuits to serve multiple functions. The same circuitry is used for both calibration during initialization and ongoing monitoring during operation, reducing the need for separate dedicated components and simplifying the overall device architecture.
Data Source
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AI summary
Embodiments of the disclosure provide a calibration circuit, a memory and a calibration method. The calibration circuit includes: a differential input circuit, configured to receive a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal having the same frequency and opposite phases, the duty cycle of the first oscillation signal and the duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output a first internal signal and a second internal signal; a comparison unit, connected to an output end of the differential input circuit, and configured to compare the duty cycle of the first internal signal and/or the duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range. According to the embodiments of the disclosure, the calibration circuit has a Duty Cycle Monitor (DCM) function and a Duty Cycle Adjust (DCA) function, and also can achieve detection and calibration on the differential input circuit.