Fully Differential Input Calibration for Common-Mode Feedthrough

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Solution Overview

Problem

Conventional current sense amplifiers suffer from common mode voltage feed through due to resistor mismatches, which is exacerbated by the small sense voltage being proportional to the common mode voltage, leading to significant distortion and inaccuracies in the digital signal.

Innovation Solution

A calibration method is employed to trim the individual resistances of resistors in a star configuration to maintain a voltage difference of approximately zero between nodes, ensuring a constant ratio among resistors to minimize common mode feed through and enhance common mode rejection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resistor matching is used to reduce common mode feed through, then common mode rejection is improved, but device complexity and calibration requirements increase

Engineering Contradiction:
Improvecommon mode rejectionVSAvoidcalibration system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing calibration during the manufacturing process to pre-adjust resistor values and minimize mismatches before the device is deployed. This advance calibration reduces common mode feed through without requiring complex real-time calibration systems during operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through on-chip calibration circuits that automatically adjust resistor values using internal resources. The calibration system uses the device's own power supply and signal paths to perform measurements and adjustments, eliminating the need for external calibration equipment and reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

2Ease of manufacture

If on-chip self-calibration is implemented, then external calibration equipment is eliminated, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecalibration process simplicityVSAvoidresistor trimming precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies partial action by implementing calibration for only the most critical resistor pairs that have the greatest impact on common mode rejection. Rather than calibrating all resistors in the circuit, the system focuses on key resistors, reducing manufacturing precision requirements while still achieving effective common mode rejection.

Inventive Principle:
Principle #16Partial or excessive action

3Object-affected harmful factors

If star configuration resistors are trimmed to maintain zero voltage difference, then common mode feed through is reduced, but measurement precision requirements increase

Engineering Contradiction:
Improvecommon mode feed throughVSAvoidvoltage difference measurement
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary calibration voltage that is applied to the star configuration nodes during the calibration process. This intermediary signal allows the system to measure and adjust resistor mismatches indirectly, reducing the measurement precision requirements compared to directly measuring small differential voltages during normal operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12556149B2Calibration of fully-differential input system
Publication Date: 2026.02.17 CIRRUS LOGIC INC
  • US12556149B2 patent drawing
  • US12556149B2 patent drawing
  • US12556149B2 patent drawing

AI summary

A method for calibrating a fully-differential input system may include determining a first voltage of a first node of the fully-differential input system, wherein the first node is coupled at the first node to a plurality of first resistors in a first star configuration, determining a second voltage of a second node of the fully-differential input system, wherein the second node is coupled at the second node to a plurality of second resistors in a second star configuration, each resistor of the plurality of second resistors corresponding to a respective resistor of the plurality of first resistors, and trimming individual resistances of the plurality of first resistors and the plurality of second resistors in order to maintain a difference of a first voltage at the first node and a second voltage of the second node at approximately zero.