Differential Input Circuit Layout for Low-Offset Fast Comparators

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Solution Overview

Problem

Circuits with comparator functions experience deviations in output value changes due to impedance variations, leading to input offset voltages, and traditional trimming techniques to adjust these voltages can deteriorate circuit responsiveness.

Innovation Solution

An input circuit with parallel differential transistor sections and a selectable cutoff section, connected to an output circuit with parallel current path sections, stabilizes current flow and reduces input offset voltages without altering total current amounts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a current source is added to adjust the input offset voltage, then the input offset voltage can be trimmed, but the circuit responsiveness deteriorates due to current amount changes affecting transistor charging time

Engineering Contradiction:
Improveinput offset voltage adjustment precisionVSAvoidcircuit responsiveness
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent changes the resistance values of trimming resistors to adjust the input offset voltage instead of changing current amounts. By varying resistance parameters in the trimming circuit, the desired voltage adjustment is achieved without affecting the current that charges transistors, thus maintaining fast responsiveness while enabling precise offset voltage trimming.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent divides the trimming function into separate resistance adjustment mechanisms independent of the main current path. Multiple trimming resistors are used to separately control different aspects of the offset voltage without interfering with the current source that determines transistor charging speed, allowing independent optimization of both precision and responsiveness.

Inventive Principle:
Principle #1Segmentation

2Reliability

If impedance variations occur in circuit elements, then the output value changes, but input offset voltage deviates from the actual input voltage difference

Engineering Contradiction:
Improveoutput accuracyVSAvoidinput offset voltage accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the input offset voltage is measured and then trimmed by adjusting resistor values. The trimming process continuously monitors the offset voltage and makes corrections until the desired accuracy is achieved, compensating for impedance variations in circuit elements and ensuring reliable output that accurately reflects the true input voltage difference.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent compensates for impedance variations by dynamically adjusting resistance parameters in the trimming circuit. By changing resistor values based on measured offset voltages, the system counteracts the effects of element impedance variations and maintains accurate input offset voltage measurement and output reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250300655A1Input circuit and semiconductor device
Publication Date: 2025.09.25 KK TOSHIBA
  • US20250300655A1 patent drawing
  • US20250300655A1 patent drawing
  • US20250300655A1 patent drawing

AI summary

According to one embodiment, an input circuit is connected to an output circuit that outputs an output value based on a first voltage and a second voltage, to which the first voltage and the second voltage are applied. The input circuit includes: a first differential transistor section including a plurality of first transistors connected in parallel with each other; a second differential transistor section including a plurality of second transistors connected in parallel with each other; and a selectable cutoff section capable of selecting a state in which a current is cut off. The output circuit includes a first current path section and a second current path section arranged in parallel with each other between ground and a power supply voltage wiring. The first differential transistor section and the second differential transistor section are arranged in parallel with each other between the ground and the power supply voltage wiring.