Differential Input Stage with Opposing Skews for Offset Trimming
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Solution Overview
Problem
Differential pairs in signal processing circuits suffer from voltage offset due to manufacturing mismatches, and existing solutions to trim this offset often require additional components that increase complexity, parasitic capacitance, or affect gain and speed.
Innovation Solution
Employing a first and second differential pair with opposing skews to control voltage offset, and adjusting the bias current with a trimming current to compensate for manufacturing variations without affecting the signal path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional components are added to trim the voltage offset of the differential pair, then the voltage offset is reduced, but the device complexity increases and parasitic capacitance is introduced
Solution Approach 1:
The input stage is segmented into two differential pairs instead of one, allowing the voltage offset compensation function to be distributed across the paired structures. This segmentation enables offset trimming through the inherent properties of the differential pairs rather than adding separate trimming components.
Solution Approach 2:
The second differential pair is designed with asymmetric transistor sizing (different width-to-length ratios) to create a deliberate current skew that opposes the manufacturing mismatch in the first differential pair. This asymmetric design allows the combined output currents to cancel out voltage offsets without requiring additional trimming components.
2Manufacturing precision
If additional components are added to trim the voltage offset, then the voltage offset is reduced, but parasitic capacitance increases affecting circuit speed
Solution Approach 1:
By segmenting the offset compensation function into the intrinsic properties of two differential pairs, the solution avoids adding discrete trimming components that would introduce parasitic capacitance. The segmented architecture maintains signal path integrity and minimizes capacitive loading.
Solution Approach 2:
The offset compensation function is merged with the signal amplification function by using the second differential pair's output currents to directly counterbalance the first differential pair's offset. This merging eliminates the need for separate trimming circuits and their associated parasitic capacitances.
3Manufacturing precision
If additional components are added to trim the voltage offset, then the voltage offset is reduced, but the gain of the circuit changes
Solution Approach 1:
Each differential pair is designed with specific local transistor sizing qualities - the first pair with matched transistors for signal amplification, and the second pair with deliberately asymmetric sizing for offset compensation. This local quality differentiation allows offset trimming without requiring global changes to the circuit gain characteristics.
Solution Approach 2:
The transistor width-to-length ratios are changed in the second differential pair to create the opposing current skew, rather than adding separate trimming components. This parameter change approach allows precise control of the compensation effect while maintaining the overall gain characteristics of the amplifier.
Data Source
AI summary
An input stage for a signal processing circuit, the input comprising: a first differential pair; and a second differential pair; wherein the first differential pair and the second differential pairs have opposing skews which controls a voltage offset of the input stage.