Differential Inverter Latch for Fast, Low-Interference Comparison
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Solution Overview
Problem
Existing latches in circuits face challenges in efficiently storing data states and avoiding inter-symbol interference, particularly in high-speed comparison circuits.
Innovation Solution
A latch design incorporating two sets of inverters, where the first inverter's signal input is connected to one latch input and the supply input is biased by the other, allowing faster state changes based on voltage differentials, with synchronized reset and latching phases to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional latch design is used, then the circuit can store data states, but the transmission speed is limited and inter-symbol interference occurs
Solution Approach 1:
The latch is divided into two separate sets of inverters (first and second sets), each processing one of the two input signals independently. This segmentation allows parallel processing of differential signals, increasing transmission speed while maintaining signal integrity and reducing interference between symbols.
Solution Approach 2:
The patent transitions from a single-input latch to a differential latch with two inputs and two outputs. By adding this dimensional aspect (differential signaling), the circuit achieves faster transmission through voltage differential detection while the complementary structure naturally reduces inter-symbol interference.
2Speed
If the supply input of the first inverter is biased by the other latch input, then faster state changes occur, but the circuit complexity increases
Solution Approach 1:
The patent merges the biasing function with the signal processing function. The second latch input serves dual purposes: as a signal input and as the bias source for the first inverter's supply input. This merging eliminates the need for separate biasing circuits, achieving fast state changes without proportionally increasing complexity.
Solution Approach 2:
Each latch input serves multiple functions: the first input is both a signal input and biases the second inverter, while the second input is both a signal input and biases the first inverter. This multi-functionality reduces the number of dedicated biasing elements needed, balancing speed improvement with circuit complexity.
Data Source
AI summary
A latch includes two outputs and two inputs where the outputs latch complementary values indicative of voltages at the latch inputs. The latch includes two sets of one or more inverters. For each set of inverters, the signal input of the first in series inverter is connected to a latch input and the output of the last in series inverter is connected to a latch output. The first in series inverters for each set of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by the other latch input. During a reset phase, the latch outputs are configured to be set to the same output value state. During a latching phase, the latch outputs are configured to be latched at complementary output value states. In some embodiments, the latch is used in a comparison circuit.