Differential Inverter Latch for Faster Complementary State Switching
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Solution Overview
Problem
Existing latches in circuits are slow in transitioning to complementary output states due to inter-symbol interference and require multiple signal nodes, which affects the speed and efficiency of data storage and comparison processes.
Innovation Solution
A latch design incorporating two sets of inverters in series, where one inverter's signal input is connected to one latch input and the supply input is biased by the other latch input, allowing faster state changes based on voltage differentials, and synchronized reset phases to avoid interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional latch designs are used, then the circuit structure is simple, but the transition speed to complementary output states is slow due to inter-symbol interference
Solution Approach 1:
The latch circuit is divided into two separate sets of inverters (first set and second set) with distinct signal paths. Each set processes one of the complementary inputs independently, segmenting the signal flow to eliminate inter-symbol interference and enable faster transition to complementary output states.
Solution Approach 2:
The invention introduces a differential dimension by using two separate inverter sets that process complementary inputs (D and D̅) through independent paths. This dimensional separation in the signal processing architecture allows simultaneous evaluation of both logic states, dramatically improving transition speed.
2Productivity
If multiple signal nodes are used in traditional latches, then the latch can store data states, but the number of signal nodes increases circuit complexity and reduces efficiency
Solution Approach 1:
The invention merges the functions of multiple traditional latch nodes into a streamlined configuration where two inverter sets share common output nodes (Q and Q̅). This consolidation reduces the total number of signal nodes while maintaining data storage capability and improving comparison efficiency through the differential architecture.
Data Source
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AI summary
A latch includes two outputs and two inputs where the outputs latch complementary values indicative of voltages at the latch inputs. The latch includes two sets of one or more inverters. For each set of inverters, the signal input of the first in series inverter is connected to a latch input and the output of the last in series inverter is connected to a latch output. The first in series inverters for each set of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by the other latch input. During a reset phase, the latch outputs are configured to be set to the same output value state. During a latching phase, the latch outputs are configured to be latched at complementary output value states. In some embodiments, the latch is used in a comparison circuit.