Differential Latch Circuit for DAC Crossover Point Control
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Solution Overview
Problem
Conventional switch drivers and differential latches in DACs face limitations in adjusting output data intersection points, leading to reduced linearity and reliability due to mismatched PMOS and NMOS width-to-length ratios and the introduction of level shift circuits, which affect current capability and inter-symbol interference.
Innovation Solution
A differential latch circuit with non-matching PMOS and NMOS width-to-length ratios, series connection of PMOS transistors in the pull-up terminal of the second-stage inverter, and a CMOS structure in the pull-down terminal, along with a level shift circuit to adjust voltage levels, enhancing flexibility in adjusting output data intersection points and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional differential latch uses matched PMOS and NMOS width-to-length ratios, then circuit symmetry is maintained, but output data intersection points cannot be precisely adjusted leading to reduced linearity
Solution Approach 1:
The patent applies asymmetry by intentionally designing non-matched width-to-length ratios for PMOS and NMOS transistors in the differential latch. Specifically, the PMOS transistors have width-to-length ratios that differ from their matched NMOS counterparts, enabling precise control over output data intersection points. This asymmetric configuration directly addresses the linearity issue by allowing independent optimization of pull-up and pull-down strengths without requiring circuit symmetry.
Solution Approach 2:
The patent implements local quality by applying different width-to-length ratio relationships to different transistor pairs within the differential latch. The first and second PMOS transistors have one width-to-length ratio relationship, while the third and fourth PMOS transistors have another relationship, allowing localized optimization of intersection point control in different parts of the circuit while maintaining overall functionality.
2Manufacturing precision
If level shift circuit is added to adjust voltage levels, then output data intersection point control is improved, but current capability is reduced and inter-symbol interference increases
Solution Approach 1:
The patent merges the voltage level adjustment function directly into the differential latch structure by integrating the level shift capability through the asymmetric PMOS/NMOS configuration. Instead of adding a separate level shift circuit that would introduce additional signal paths and potential interference, the level adjustment is achieved through the transistor ratio design itself, combining multiple functions into a single unified structure that maintains signal integrity.
3Ease of operation
If three stages of latches are used for data synchronization, then data synchronization is achieved, but device complexity and inter-symbol interference increase
Solution Approach 1:
The patent extracts and eliminates redundant latch stages from the conventional three-stage configuration. By using the asymmetric PMOS/NMOS differential latch with integrated level shifting capability, the patent reduces the number of discrete latch stages needed while maintaining effective data synchronization. This extraction of unnecessary components simplifies the overall circuit architecture and reduces inter-symbol interference associated with multiple cascaded latch stages.
Data Source
AI summary
Provided are a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit includes: a first-stage differential latch circuit (I), a second-stage differential inverter circuit (II), and a low-level shift circuit, a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit (II) includes a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor (M9) and a second PMOS transistor (M10), a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit (II) includes a third PMOS transistor (M15) and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor (M11), and a circuit structure of a differential negative terminal of the first-stage differential latch circuit (I) is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit (I).