Differential Level-Shifter Circuit for Low Jitter Across PVT Corners
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Solution Overview
Problem
Current level-shifters, particularly those converting CIVIL to CMOS signals, face issues with elevated jitter and power/current penalties across different process, voltage, and temperature (PVT) corners, and often rely on single inverter stages for non-differential applications, degrading performance.
Innovation Solution
A level-shifter circuit comprising a pre-driver stage with diode connected MOS devices and resistor loads, coupled with output stages that include MOS devices and resistor loads, is designed to generate differential outputs with controlled current consumption and voltage settings, minimizing jitter and power variations across PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level-shifters are used to convert CIVIL to CMOS signals, then level conversion is achieved, but jitter performance deteriorates and power consumption increases across PVT corners
Solution Approach 1:
The level-shifter is divided into multiple independent stages: a pre-driver stage and two output stages. Each stage is optimized for specific functions, allowing better control over power consumption and signal integrity separately, rather than using a single conventional stage that compromises both.
Solution Approach 2:
Different stages use different circuit topologies and device sizing strategies tailored to their specific functions. The pre-driver stage uses diode-connected MOS devices with specific resistor ratios, while output stages use different configurations, allowing each part to be optimized for its local requirements rather than using a uniform design.
2Reliability
If conventional level-shifters are used to convert CIVIL to CMOS signals, then level conversion is achieved, but jitter performance deteriorates
Solution Approach 1:
By segmenting the level-shifter into pre-driver and output stages, each stage can be optimized for jitter reduction. The pre-driver stage prepares signals with controlled transitions, while output stages provide buffered differential outputs, collectively achieving low jitter performance that a single conventional stage cannot provide.
Solution Approach 2:
The patent employs specific parameter ratios (resistor ratios, MOS device width ratios) that are optimized to minimize jitter. These parameter changes in device dimensions and component values are carefully selected to control signal transitions and reduce timing variations across PVT corners.
3Device complexity
If single inverter stages are used for non-differential applications, then circuit complexity is reduced, but performance deteriorates
Solution Approach 1:
Even for non-differential applications, the circuit uses segmented stages (pre-driver plus output stage) rather than a single inverter. This segmentation provides better signal integrity and performance while maintaining reasonable complexity through modular design.
Solution Approach 2:
The multi-stage architecture is designed to be universal, working effectively for both differential and non-differential applications. The same basic structure provides performance benefits across different application types, reducing the need for application-specific design modifications.
Data Source
AI summary
One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.