Differential Level Shifter for Wider Voltage Split Range
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Solution Overview
Problem
Traditional level shifters face limitations in supply voltage split range, which restricts the voltage range difference between the high and low voltage domains, impacting memory access time and power consumption in devices like SRAM.
Innovation Solution
Incorporating a differential sensing transistor pair and an enable circuit with PMOS and NMOS transistors, allowing the level shifter to shift signals from a low voltage domain to a higher voltage domain, thereby enlarging the supply voltage split range and optimizing SRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional level shifters are used, then the device structure is simple, but the supply voltage split range is limited
Solution Approach 1:
The level shifter is divided into multiple functional blocks: a first level shifter for shifting from low voltage domain to intermediate voltage domain, and a second level shifter for shifting from intermediate voltage domain to high voltage domain. This segmentation allows the system to achieve a larger overall voltage split range by cascading multiple smaller voltage shifts, while keeping each individual block relatively simple in structure.
Solution Approach 2:
The patent implements a nested architecture where the first level shifter is embedded within the second level shifter structure. The intermediate voltage domain serves as a bridge, with the first level shifter operating in the lower voltage range and the second level shifter operating in the higher voltage range, creating a nested voltage domain structure that expands the total voltage split range.
2Speed
If the supply voltage split range is enlarged, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic control mechanisms where the level shifters are enabled only when voltage domain transitions are required. The dynamic voltage domain switching allows the system to adaptively activate level shifting functionality based on operational needs, ensuring fast memory access when voltage transitions are necessary while minimizing power consumption by keeping level shifters inactive during same-domain operations.
Solution Approach 2:
The system dynamically changes operating parameters by switching between different voltage domains (low, intermediate, high) based on the operational requirements. This parameter change approach allows the memory device to optimize performance by operating in high-voltage domains for fast access when needed, while returning to low-voltage domains for normal operations to reduce power consumption.
3Reliability
If the supply voltage split range is increased, then device yield is improved, but circuit complexity increases
Solution Approach 1:
By segmenting the voltage shifting function into multiple dedicated level shifters, each operating within a specific voltage range, the patent achieves better device yield. Each segment can be independently optimized and tested, improving manufacturing reliability while the modular structure helps manage overall circuit complexity through systematic organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances memory access speed while minimizing power consumption by enabling efficient signal shifting across a larger voltage range, improving device yield and performance.
Implementation Method 1
a PMOS transistor coupled between the first output terminal and the second output terminal and having a gate terminal connected to receive the clock signal, the PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the clock signal
Implementation Method 2
a first NMOS sensing transistor and a second NMOS sensing transistor having a common source terminal, wherein a drain terminal of the first NMOS sensing transistor is coupled to the first inverter, a gate terminal of the first NMOS sensing transistor is configured to receive the input signal, a drain terminal of the second NMOS sensing transistor is coupled to the second inverter, and a gate terminal of the second NMOS sensing transistor is configured to receive the complement of the input signal
Data Source
AI summary
A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.